Search

Cynthia H. Britt

Examiner (ID: 11869)

Most Active Art Unit
2117
Art Unit(s)
2117, 2111, 2133, 2138
Total Applications
1844
Issued Applications
1687
Pending Applications
80
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12316542 [patent_doc_number] => 09941904 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-10 [patent_title] => Decoding method, decoding apparatus, and communications system [patent_app_type] => utility [patent_app_number] => 14/873502 [patent_app_country] => US [patent_app_date] => 2015-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9936 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14873502 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/873502
Decoding method, decoding apparatus, and communications system Oct 1, 2015 Issued
Array ( [id] => 10667665 [patent_doc_number] => 20160013811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'CODING AND DECODING METHOD AND DEVICE, AND SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/864338 [patent_app_country] => US [patent_app_date] => 2015-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 16131 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14864338 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/864338
Coding and decoding method and device, and system Sep 23, 2015 Issued
Array ( [id] => 11027458 [patent_doc_number] => 20160224414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'DUAL IN-LINE MEMORY MODULES (DIMMs) SUPPORTING STORAGE OF A DATA INDICATOR(S) IN AN ERROR CORRECTING CODE (ECC) STORAGE UNIT DEDICATED TO STORING AN ECC' [patent_app_type] => utility [patent_app_number] => 14/857491 [patent_app_country] => US [patent_app_date] => 2015-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11688 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14857491 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/857491
Dual in-line memory modules (DIMMs) supporting storage of a data indicator(s) in an error correcting code (ECC) storage unit dedicated to storing an ECC Sep 16, 2015 Issued
Array ( [id] => 10657763 [patent_doc_number] => 20160003907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-07 [patent_title] => 'CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELECTIVE COMPACTION OF TEST RESPONSES' [patent_app_type] => utility [patent_app_number] => 14/853412 [patent_app_country] => US [patent_app_date] => 2015-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 11369 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14853412 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/853412
Continuous application and decompression of test patterns and selective compaction of test responses Sep 13, 2015 Issued
Array ( [id] => 11390510 [patent_doc_number] => 09551748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-24 [patent_title] => 'Double data rate addressable tap interface with shadow protocol circuitry' [patent_app_type] => utility [patent_app_number] => 14/853255 [patent_app_country] => US [patent_app_date] => 2015-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 34 [patent_no_of_words] => 9643 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14853255 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/853255
Double data rate addressable tap interface with shadow protocol circuitry Sep 13, 2015 Issued
Array ( [id] => 10723807 [patent_doc_number] => 20160069955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-10 [patent_title] => 'SHADOW ACCESS PORT METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/853315 [patent_app_country] => US [patent_app_date] => 2015-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 13089 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14853315 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/853315
IC output circuit with test data and shadow data inputs Sep 13, 2015 Issued
Array ( [id] => 10657765 [patent_doc_number] => 20160003909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-07 [patent_title] => 'REDUCED SIGNALING INTERFACE METHOD & APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/853103 [patent_app_country] => US [patent_app_date] => 2015-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 16748 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14853103 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/853103
TAP addressable circuit with bi-directional TMS and second signal lead Sep 13, 2015 Issued
Array ( [id] => 11500748 [patent_doc_number] => 20170074934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'REDUCING POWER REQUIREMENTS AND SWITCHING DURING LOGIC BUILT-IN-SELF-TEST AND SCAN TEST' [patent_app_type] => utility [patent_app_number] => 14/851174 [patent_app_country] => US [patent_app_date] => 2015-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8030 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14851174 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/851174
Reducing power requirements and switching during logic built-in-self-test and scan test Sep 10, 2015 Issued
Array ( [id] => 10492941 [patent_doc_number] => 20150377963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'IEEE 1149.1 AND P1500 TEST INTERFACES COMBINED CIRCUITS AND PROCESSES' [patent_app_type] => utility [patent_app_number] => 14/849832 [patent_app_country] => US [patent_app_date] => 2015-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 60 [patent_no_of_words] => 19955 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14849832 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/849832
IR enabled gating of TAP and WSP shift, capture, transfer Sep 9, 2015 Issued
Array ( [id] => 14206675 [patent_doc_number] => 10270470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => Polar code decoding method and decoder [patent_app_type] => utility [patent_app_number] => 14/845565 [patent_app_country] => US [patent_app_date] => 2015-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 10210 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14845565 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/845565
Polar code decoding method and decoder Sep 3, 2015 Issued
Array ( [id] => 11320285 [patent_doc_number] => 09519025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-13 [patent_title] => 'Tap and aux circuitry with multiplexers on TDI, TDO, AUXI/O' [patent_app_type] => utility [patent_app_number] => 14/837786 [patent_app_country] => US [patent_app_date] => 2015-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 35 [patent_no_of_words] => 14135 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14837786 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/837786
Tap and aux circuitry with multiplexers on TDI, TDO, AUXI/O Aug 26, 2015 Issued
Array ( [id] => 12109751 [patent_doc_number] => 09866243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-09 [patent_title] => 'Forward error correction codeword synchronization method, device, and system' [patent_app_type] => utility [patent_app_number] => 14/836597 [patent_app_country] => US [patent_app_date] => 2015-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 11395 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14836597 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/836597
Forward error correction codeword synchronization method, device, and system Aug 25, 2015 Issued
Array ( [id] => 11245379 [patent_doc_number] => 09471422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-18 [patent_title] => 'Adaptive error correction in a memory system' [patent_app_type] => utility [patent_app_number] => 14/834469 [patent_app_country] => US [patent_app_date] => 2015-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6402 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14834469 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/834469
Adaptive error correction in a memory system Aug 24, 2015 Issued
Array ( [id] => 10470970 [patent_doc_number] => 20150355987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'AT-SPEED TEST ACCESS PORT OPERATIONS' [patent_app_type] => utility [patent_app_number] => 14/830244 [patent_app_country] => US [patent_app_date] => 2015-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 13137 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14830244 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/830244
At speed tap with dual port router and command circuit Aug 18, 2015 Issued
Array ( [id] => 10461263 [patent_doc_number] => 20150346278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'JTAG BUS COMMUNICATION METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/822301 [patent_app_country] => US [patent_app_date] => 2015-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11693 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14822301 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/822301
Bi-directional TCK lead carrying TCK and frame data in/out signal Aug 9, 2015 Issued
Array ( [id] => 10470260 [patent_doc_number] => 20150355276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'ADAPTING SCAN ARCHITECTURES FOR LOW POWER OPERATION' [patent_app_type] => utility [patent_app_number] => 14/822328 [patent_app_country] => US [patent_app_date] => 2015-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13522 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14822328 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/822328
Divided scan path cells with first and state hold multiplexers Aug 9, 2015 Issued
Array ( [id] => 12296133 [patent_doc_number] => 09935735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-03 [patent_title] => Multiuse data channel [patent_app_type] => utility [patent_app_number] => 14/820137 [patent_app_country] => US [patent_app_date] => 2015-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14820137 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/820137
Multiuse data channel Aug 5, 2015 Issued
Array ( [id] => 11763813 [patent_doc_number] => 09372230 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-21 [patent_title] => 'Substrate with state machine circuitry and tap state monitor circuitry' [patent_app_type] => utility [patent_app_number] => 14/815396 [patent_app_country] => US [patent_app_date] => 2015-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 32 [patent_no_of_words] => 6219 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14815396 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/815396
Substrate with state machine circuitry and tap state monitor circuitry Jul 30, 2015 Issued
Array ( [id] => 12459354 [patent_doc_number] => 09985659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-29 [patent_title] => Error correction processing circuit in memory and error correction processing method [patent_app_type] => utility [patent_app_number] => 14/810749 [patent_app_country] => US [patent_app_date] => 2015-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5579 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14810749 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/810749
Error correction processing circuit in memory and error correction processing method Jul 27, 2015 Issued
Array ( [id] => 10453451 [patent_doc_number] => 20150338465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'MULTIPLE-CAPTURE DFT SYSTEM FOR DETECTING OR LOCATING CROSSING CLOCK-DOMAIN FAULTS DURING SCAN-TEST' [patent_app_type] => utility [patent_app_number] => 14/804749 [patent_app_country] => US [patent_app_date] => 2015-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 15480 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14804749 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/804749
Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test Jul 20, 2015 Issued
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