Search

Cynthia H. Britt

Examiner (ID: 18558, Phone: (571)272-3815 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2133, 2138, 2117, 2111
Total Applications
1856
Issued Applications
1695
Pending Applications
82
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10277918 [patent_doc_number] => 20150162915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-11 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT AND POWER-SUPPLY VOLTAGE ADAPTIVE CONTROL SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/620528 [patent_app_country] => US [patent_app_date] => 2015-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 13408 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14620528 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/620528
Semiconductor integrated circuit and power-supply voltage adaptive control system Feb 11, 2015 Issued
Array ( [id] => 10351815 [patent_doc_number] => 20150236820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-20 [patent_title] => 'LOW LATENCY, AUTOMATIC REPEAT REQUEST (\"ARQ\") IN A MULTI-DEVICE COMMUNICATIONS LINK' [patent_app_type] => utility [patent_app_number] => 14/619973 [patent_app_country] => US [patent_app_date] => 2015-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4966 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14619973 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/619973
Low latency, automatic repeat request (“ARQ”) in a multi-device communications link Feb 10, 2015 Issued
Array ( [id] => 10616627 [patent_doc_number] => 09336072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-10 [patent_title] => 'Event group extensions, systems, and methods' [patent_app_type] => utility [patent_app_number] => 14/617814 [patent_app_country] => US [patent_app_date] => 2015-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8352 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14617814 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/617814
Event group extensions, systems, and methods Feb 8, 2015 Issued
Array ( [id] => 10344435 [patent_doc_number] => 20150229440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'FORWARD ERROR CORRECTION (FEC) DATA TRANSMISSION SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/616616 [patent_app_country] => US [patent_app_date] => 2015-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9129 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14616616 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/616616
Forward error correction (FEC) data transmission system Feb 5, 2015 Issued
Array ( [id] => 10561758 [patent_doc_number] => 09285425 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-15 [patent_title] => 'Test access mechanism, controller, selector, scan router, external data bus' [patent_app_type] => utility [patent_app_number] => 14/612833 [patent_app_country] => US [patent_app_date] => 2015-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 56 [patent_no_of_words] => 20885 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14612833 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/612833
Test access mechanism, controller, selector, scan router, external data bus Feb 2, 2015 Issued
Array ( [id] => 10194071 [patent_doc_number] => 09222975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-29 [patent_title] => 'IC core DDR separate test controller, selector, scan router circuitry' [patent_app_type] => utility [patent_app_number] => 14/612786 [patent_app_country] => US [patent_app_date] => 2015-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 63 [patent_no_of_words] => 24067 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14612786 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/612786
IC core DDR separate test controller, selector, scan router circuitry Feb 2, 2015 Issued
Array ( [id] => 11206233 [patent_doc_number] => 09435859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'Interposer capture shift update cell between functional and test data' [patent_app_type] => utility [patent_app_number] => 14/612748 [patent_app_country] => US [patent_app_date] => 2015-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 66 [patent_no_of_words] => 14508 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14612748 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/612748
Interposer capture shift update cell between functional and test data Feb 2, 2015 Issued
Array ( [id] => 10597970 [patent_doc_number] => 09319069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-19 [patent_title] => 'Reduced complexity non-binary LDPC decoding algorithm' [patent_app_type] => utility [patent_app_number] => 14/607039 [patent_app_country] => US [patent_app_date] => 2015-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 10890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14607039 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/607039
Reduced complexity non-binary LDPC decoding algorithm Jan 26, 2015 Issued
Array ( [id] => 10283494 [patent_doc_number] => 20150168492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-18 [patent_title] => 'TEST ACCESS PORT WITH ADDRESS AND COMMAND CAPABILITY' [patent_app_type] => utility [patent_app_number] => 14/605728 [patent_app_country] => US [patent_app_date] => 2015-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 10456 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14605728 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/605728
Addressable tap address, state monitor, decode and TMS gating circuitry Jan 25, 2015 Issued
Array ( [id] => 10250039 [patent_doc_number] => 20150135035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/601664 [patent_app_country] => US [patent_app_date] => 2015-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5927 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14601664 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/601664
Semiconductor memory device and method of controlling the same Jan 20, 2015 Issued
Array ( [id] => 10245490 [patent_doc_number] => 20150130485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'MODULATED TEST MESSAGING FROM DEDICATED TEST CIRCUITRY TO POWER TERMINAL' [patent_app_type] => utility [patent_app_number] => 14/599849 [patent_app_country] => US [patent_app_date] => 2015-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 12654 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14599849 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/599849
Test messaging demodulate and modulate on separate power pads Jan 18, 2015 Issued
Array ( [id] => 13284537 [patent_doc_number] => 10153863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-11 [patent_title] => Method and device for transmitting and receiving packet in communication system [patent_app_type] => utility [patent_app_number] => 15/111322 [patent_app_country] => US [patent_app_date] => 2015-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 30 [patent_no_of_words] => 14975 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15111322 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/111322
Method and device for transmitting and receiving packet in communication system Jan 12, 2015 Issued
Array ( [id] => 10230996 [patent_doc_number] => 20150115990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-30 [patent_title] => 'DIE STACK TEST ARCHITECTURE AND METHOD' [patent_app_type] => utility [patent_app_number] => 14/590502 [patent_app_country] => US [patent_app_date] => 2015-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 4985 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14590502 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/590502
IC top/bottom surfaces coupled to test, scan, and comparator circuitry Jan 5, 2015 Issued
Array ( [id] => 10230996 [patent_doc_number] => 20150115990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-30 [patent_title] => 'DIE STACK TEST ARCHITECTURE AND METHOD' [patent_app_type] => utility [patent_app_number] => 14/590502 [patent_app_country] => US [patent_app_date] => 2015-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 4985 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14590502 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/590502
IC top/bottom surfaces coupled to test, scan, and comparator circuitry Jan 5, 2015 Issued
Array ( [id] => 10517714 [patent_doc_number] => 09244762 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-01-26 [patent_title] => 'Method and apparatus for flexible buffers in an XOR engine' [patent_app_type] => utility [patent_app_number] => 14/584970 [patent_app_country] => US [patent_app_date] => 2014-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4354 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14584970 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/584970
Method and apparatus for flexible buffers in an XOR engine Dec 28, 2014 Issued
Array ( [id] => 10759048 [patent_doc_number] => 20160105201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-14 [patent_title] => 'METHOD AND INTERLEAVING APPARATUS FOR INTERLEAVING FOR ERROR DISPERSION AND COMPUTER READABLE RECORDING MEDIUM FOR PERFORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/583025 [patent_app_country] => US [patent_app_date] => 2014-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6370 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14583025 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/583025
Method and interleaving apparatus for interleaving for error dispersion and computer readable recording medium for performing the same Dec 23, 2014 Issued
Array ( [id] => 10825890 [patent_doc_number] => 20160172058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'SYSTEM AND METHOD FOR HANDLING MEMORY REPAIR DATA' [patent_app_type] => utility [patent_app_number] => 14/568091 [patent_app_country] => US [patent_app_date] => 2014-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4792 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14568091 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/568091
System and method for handling memory repair data Dec 10, 2014 Issued
Array ( [id] => 10188360 [patent_doc_number] => 09217773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-22 [patent_title] => 'Addressable tap selection aux i/o, linking, address, instruction, control circuitry' [patent_app_type] => utility [patent_app_number] => 14/567299 [patent_app_country] => US [patent_app_date] => 2014-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 55 [patent_no_of_words] => 21284 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14567299 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/567299
Addressable tap selection aux i/o, linking, address, instruction, control circuitry Dec 10, 2014 Issued
Array ( [id] => 10816195 [patent_doc_number] => 20160162356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'METHODS AND SYSTEMS FOR IMPLEMENTING REDUNDANCY IN MEMORY CONTROLLERS' [patent_app_type] => utility [patent_app_number] => 14/564798 [patent_app_country] => US [patent_app_date] => 2014-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7388 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14564798 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/564798
Methods and systems for implementing redundancy in memory controllers Dec 8, 2014 Issued
Array ( [id] => 10816191 [patent_doc_number] => 20160162352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'SYSTEMS AND METHODS FOR ADAPTIVE ERROR CORRECTIVE CODE MECHANISMS' [patent_app_type] => utility [patent_app_number] => 14/560767 [patent_app_country] => US [patent_app_date] => 2014-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5656 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14560767 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/560767
Systems and methods for adaptive error corrective code mechanisms Dec 3, 2014 Issued
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