Search

Cynthia H. Britt

Examiner (ID: 11869)

Most Active Art Unit
2117
Art Unit(s)
2117, 2111, 2133, 2138
Total Applications
1844
Issued Applications
1687
Pending Applications
80
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11466577 [patent_doc_number] => 09583216 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-28 [patent_title] => 'MBIST device for use with ECC-protected memories' [patent_app_type] => utility [patent_app_number] => 14/656966 [patent_app_country] => US [patent_app_date] => 2015-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9079 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14656966 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/656966
MBIST device for use with ECC-protected memories Mar 12, 2015 Issued
Array ( [id] => 10561753 [patent_doc_number] => 09285421 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-15 [patent_title] => 'Serializer/deserializer and method for transferring data between an integrated circuit and a test interface' [patent_app_type] => utility [patent_app_number] => 14/643083 [patent_app_country] => US [patent_app_date] => 2015-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 8855 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14643083 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/643083
Serializer/deserializer and method for transferring data between an integrated circuit and a test interface Mar 9, 2015 Issued
Array ( [id] => 10293308 [patent_doc_number] => 20150178307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'DATA DEDUPLICATION USING CRC-SEED DIFFERENTIATION BETWEEN DATA AND STUBS' [patent_app_type] => utility [patent_app_number] => 14/637169 [patent_app_country] => US [patent_app_date] => 2015-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4479 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14637169 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/637169
Data deduplication using CRC-seed differentiation between data and stubs Mar 2, 2015 Issued
Array ( [id] => 10292324 [patent_doc_number] => 20150177323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'SCAN TEST METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/636892 [patent_app_country] => US [patent_app_date] => 2015-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 22231 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14636892 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/636892
Tap clock and enable control of scan register, flip-flop, comparator Mar 2, 2015 Issued
Array ( [id] => 11539306 [patent_doc_number] => 09613721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-04 [patent_title] => 'Semiconductor memory capable of performing through-chip via test and system using the same' [patent_app_type] => utility [patent_app_number] => 14/636917 [patent_app_country] => US [patent_app_date] => 2015-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5043 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14636917 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/636917
Semiconductor memory capable of performing through-chip via test and system using the same Mar 2, 2015 Issued
Array ( [id] => 11057101 [patent_doc_number] => 20160254063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-01 [patent_title] => 'DYNAMIC APPROXIMATE STORAGE FOR CUSTOM APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 14/633787 [patent_app_country] => US [patent_app_date] => 2015-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9197 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14633787 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/633787
Dynamic approximate storage for custom applications Feb 26, 2015 Issued
Array ( [id] => 11700740 [patent_doc_number] => 09690656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-27 [patent_title] => 'Data encoding on single-level and variable multi-level cell storage' [patent_app_type] => utility [patent_app_number] => 14/633874 [patent_app_country] => US [patent_app_date] => 2015-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 12221 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14633874 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/633874
Data encoding on single-level and variable multi-level cell storage Feb 26, 2015 Issued
Array ( [id] => 11213761 [patent_doc_number] => 09442796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-13 [patent_title] => 'Memory controller supporting rate-compatible punctured codes' [patent_app_type] => utility [patent_app_number] => 14/629228 [patent_app_country] => US [patent_app_date] => 2015-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5219 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14629228 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/629228
Memory controller supporting rate-compatible punctured codes Feb 22, 2015 Issued
Array ( [id] => 10643659 [patent_doc_number] => 09360521 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-07 [patent_title] => 'Programmable access test compression architecture input and output shift registers' [patent_app_type] => utility [patent_app_number] => 14/625351 [patent_app_country] => US [patent_app_date] => 2015-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 45 [patent_no_of_words] => 13994 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14625351 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/625351
Programmable access test compression architecture input and output shift registers Feb 17, 2015 Issued
Array ( [id] => 11774505 [patent_doc_number] => 09383410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-05 [patent_title] => 'Inverted TCK access port selector having resets selecting one tap' [patent_app_type] => utility [patent_app_number] => 14/625378 [patent_app_country] => US [patent_app_date] => 2015-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 58 [patent_no_of_words] => 17835 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14625378 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/625378
Inverted TCK access port selector having resets selecting one tap Feb 17, 2015 Issued
Array ( [id] => 10277918 [patent_doc_number] => 20150162915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-11 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT AND POWER-SUPPLY VOLTAGE ADAPTIVE CONTROL SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/620528 [patent_app_country] => US [patent_app_date] => 2015-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 13408 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14620528 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/620528
Semiconductor integrated circuit and power-supply voltage adaptive control system Feb 11, 2015 Issued
Array ( [id] => 10351815 [patent_doc_number] => 20150236820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-20 [patent_title] => 'LOW LATENCY, AUTOMATIC REPEAT REQUEST (\"ARQ\") IN A MULTI-DEVICE COMMUNICATIONS LINK' [patent_app_type] => utility [patent_app_number] => 14/619973 [patent_app_country] => US [patent_app_date] => 2015-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4966 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14619973 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/619973
Low latency, automatic repeat request (“ARQ”) in a multi-device communications link Feb 10, 2015 Issued
Array ( [id] => 10616627 [patent_doc_number] => 09336072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-10 [patent_title] => 'Event group extensions, systems, and methods' [patent_app_type] => utility [patent_app_number] => 14/617814 [patent_app_country] => US [patent_app_date] => 2015-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8352 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14617814 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/617814
Event group extensions, systems, and methods Feb 8, 2015 Issued
Array ( [id] => 10344435 [patent_doc_number] => 20150229440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'FORWARD ERROR CORRECTION (FEC) DATA TRANSMISSION SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/616616 [patent_app_country] => US [patent_app_date] => 2015-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9129 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14616616 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/616616
Forward error correction (FEC) data transmission system Feb 5, 2015 Issued
Array ( [id] => 10194071 [patent_doc_number] => 09222975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-29 [patent_title] => 'IC core DDR separate test controller, selector, scan router circuitry' [patent_app_type] => utility [patent_app_number] => 14/612786 [patent_app_country] => US [patent_app_date] => 2015-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 63 [patent_no_of_words] => 24067 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14612786 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/612786
IC core DDR separate test controller, selector, scan router circuitry Feb 2, 2015 Issued
Array ( [id] => 11206233 [patent_doc_number] => 09435859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'Interposer capture shift update cell between functional and test data' [patent_app_type] => utility [patent_app_number] => 14/612748 [patent_app_country] => US [patent_app_date] => 2015-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 66 [patent_no_of_words] => 14508 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14612748 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/612748
Interposer capture shift update cell between functional and test data Feb 2, 2015 Issued
Array ( [id] => 10561758 [patent_doc_number] => 09285425 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-15 [patent_title] => 'Test access mechanism, controller, selector, scan router, external data bus' [patent_app_type] => utility [patent_app_number] => 14/612833 [patent_app_country] => US [patent_app_date] => 2015-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 56 [patent_no_of_words] => 20885 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14612833 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/612833
Test access mechanism, controller, selector, scan router, external data bus Feb 2, 2015 Issued
Array ( [id] => 10597970 [patent_doc_number] => 09319069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-19 [patent_title] => 'Reduced complexity non-binary LDPC decoding algorithm' [patent_app_type] => utility [patent_app_number] => 14/607039 [patent_app_country] => US [patent_app_date] => 2015-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 10890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14607039 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/607039
Reduced complexity non-binary LDPC decoding algorithm Jan 26, 2015 Issued
Array ( [id] => 10283494 [patent_doc_number] => 20150168492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-18 [patent_title] => 'TEST ACCESS PORT WITH ADDRESS AND COMMAND CAPABILITY' [patent_app_type] => utility [patent_app_number] => 14/605728 [patent_app_country] => US [patent_app_date] => 2015-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 10456 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14605728 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/605728
Addressable tap address, state monitor, decode and TMS gating circuitry Jan 25, 2015 Issued
Array ( [id] => 10250039 [patent_doc_number] => 20150135035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/601664 [patent_app_country] => US [patent_app_date] => 2015-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5927 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14601664 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/601664
Semiconductor memory device and method of controlling the same Jan 20, 2015 Issued
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