Search

Cynthia H. Britt

Examiner (ID: 11869)

Most Active Art Unit
2117
Art Unit(s)
2117, 2111, 2133, 2138
Total Applications
1844
Issued Applications
1687
Pending Applications
80
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10245490 [patent_doc_number] => 20150130485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'MODULATED TEST MESSAGING FROM DEDICATED TEST CIRCUITRY TO POWER TERMINAL' [patent_app_type] => utility [patent_app_number] => 14/599849 [patent_app_country] => US [patent_app_date] => 2015-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 12654 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14599849 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/599849
Test messaging demodulate and modulate on separate power pads Jan 18, 2015 Issued
Array ( [id] => 13284537 [patent_doc_number] => 10153863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-11 [patent_title] => Method and device for transmitting and receiving packet in communication system [patent_app_type] => utility [patent_app_number] => 15/111322 [patent_app_country] => US [patent_app_date] => 2015-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 30 [patent_no_of_words] => 14975 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15111322 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/111322
Method and device for transmitting and receiving packet in communication system Jan 12, 2015 Issued
Array ( [id] => 10230996 [patent_doc_number] => 20150115990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-30 [patent_title] => 'DIE STACK TEST ARCHITECTURE AND METHOD' [patent_app_type] => utility [patent_app_number] => 14/590502 [patent_app_country] => US [patent_app_date] => 2015-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 4985 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14590502 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/590502
IC top/bottom surfaces coupled to test, scan, and comparator circuitry Jan 5, 2015 Issued
Array ( [id] => 10230996 [patent_doc_number] => 20150115990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-30 [patent_title] => 'DIE STACK TEST ARCHITECTURE AND METHOD' [patent_app_type] => utility [patent_app_number] => 14/590502 [patent_app_country] => US [patent_app_date] => 2015-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 4985 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14590502 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/590502
IC top/bottom surfaces coupled to test, scan, and comparator circuitry Jan 5, 2015 Issued
Array ( [id] => 10517714 [patent_doc_number] => 09244762 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-01-26 [patent_title] => 'Method and apparatus for flexible buffers in an XOR engine' [patent_app_type] => utility [patent_app_number] => 14/584970 [patent_app_country] => US [patent_app_date] => 2014-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4354 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14584970 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/584970
Method and apparatus for flexible buffers in an XOR engine Dec 28, 2014 Issued
Array ( [id] => 10759048 [patent_doc_number] => 20160105201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-14 [patent_title] => 'METHOD AND INTERLEAVING APPARATUS FOR INTERLEAVING FOR ERROR DISPERSION AND COMPUTER READABLE RECORDING MEDIUM FOR PERFORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/583025 [patent_app_country] => US [patent_app_date] => 2014-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6370 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14583025 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/583025
Method and interleaving apparatus for interleaving for error dispersion and computer readable recording medium for performing the same Dec 23, 2014 Issued
Array ( [id] => 10188360 [patent_doc_number] => 09217773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-22 [patent_title] => 'Addressable tap selection aux i/o, linking, address, instruction, control circuitry' [patent_app_type] => utility [patent_app_number] => 14/567299 [patent_app_country] => US [patent_app_date] => 2014-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 55 [patent_no_of_words] => 21284 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14567299 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/567299
Addressable tap selection aux i/o, linking, address, instruction, control circuitry Dec 10, 2014 Issued
Array ( [id] => 10825890 [patent_doc_number] => 20160172058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'SYSTEM AND METHOD FOR HANDLING MEMORY REPAIR DATA' [patent_app_type] => utility [patent_app_number] => 14/568091 [patent_app_country] => US [patent_app_date] => 2014-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4792 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14568091 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/568091
System and method for handling memory repair data Dec 10, 2014 Issued
Array ( [id] => 10816195 [patent_doc_number] => 20160162356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'METHODS AND SYSTEMS FOR IMPLEMENTING REDUNDANCY IN MEMORY CONTROLLERS' [patent_app_type] => utility [patent_app_number] => 14/564798 [patent_app_country] => US [patent_app_date] => 2014-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7388 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14564798 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/564798
Methods and systems for implementing redundancy in memory controllers Dec 8, 2014 Issued
Array ( [id] => 11207005 [patent_doc_number] => 09436632 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'Accessing data stored in a command/address register device' [patent_app_type] => utility [patent_app_number] => 14/560976 [patent_app_country] => US [patent_app_date] => 2014-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8350 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14560976 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/560976
Accessing data stored in a command/address register device Dec 3, 2014 Issued
Array ( [id] => 10816191 [patent_doc_number] => 20160162352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'SYSTEMS AND METHODS FOR ADAPTIVE ERROR CORRECTIVE CODE MECHANISMS' [patent_app_type] => utility [patent_app_number] => 14/560767 [patent_app_country] => US [patent_app_date] => 2014-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5656 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14560767 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/560767
Systems and methods for adaptive error corrective code mechanisms Dec 3, 2014 Issued
Array ( [id] => 10615938 [patent_doc_number] => 09335374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-10 [patent_title] => 'Dynamic shift for test pattern compression' [patent_app_type] => utility [patent_app_number] => 14/557739 [patent_app_country] => US [patent_app_date] => 2014-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 6186 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14557739 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/557739
Dynamic shift for test pattern compression Dec 1, 2014 Issued
Array ( [id] => 9933921 [patent_doc_number] => 20150082114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-19 [patent_title] => 'WIRELESS RELAY APPARATUS, WIRELESS RECEIVING APPARATUS, AND DECODING METHOD' [patent_app_type] => utility [patent_app_number] => 14/554204 [patent_app_country] => US [patent_app_date] => 2014-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7177 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14554204 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/554204
Wireless relay apparatus, wireless receiving apparatus, and decoding method Nov 25, 2014 Issued
Array ( [id] => 9933918 [patent_doc_number] => 20150082110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-19 [patent_title] => '3D STACKED DIE TEST ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 14/547830 [patent_app_country] => US [patent_app_date] => 2014-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6996 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14547830 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/547830
IC tap with dual port router and additional update input Nov 18, 2014 Issued
Array ( [id] => 10258194 [patent_doc_number] => 20150143191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'SHADOW ACCESS PORT METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/543411 [patent_app_country] => US [patent_app_date] => 2014-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 13051 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14543411 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/543411
Tap and shadow access port output circuitry with clock doubler Nov 16, 2014 Issued
Array ( [id] => 11795163 [patent_doc_number] => 09404969 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-02 [patent_title] => 'Method and apparatus for efficient hierarchical chip testing and diagnostics with support for partially bad dies' [patent_app_type] => utility [patent_app_number] => 14/530218 [patent_app_country] => US [patent_app_date] => 2014-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7848 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14530218 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/530218
Method and apparatus for efficient hierarchical chip testing and diagnostics with support for partially bad dies Oct 30, 2014 Issued
Array ( [id] => 10472033 [patent_doc_number] => 20150357050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'Reliability Screening of Ferroelectric Memories in Integrated Circuits' [patent_app_type] => utility [patent_app_number] => 14/519894 [patent_app_country] => US [patent_app_date] => 2014-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8329 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14519894 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/519894
Reliability screening of ferroelectric memories in integrated circuits Oct 20, 2014 Issued
Array ( [id] => 10136982 [patent_doc_number] => 09170300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-27 [patent_title] => 'Linking circuitry selectively coupling TDI/TDO with first and second domains' [patent_app_type] => utility [patent_app_number] => 14/514911 [patent_app_country] => US [patent_app_date] => 2014-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 46 [patent_no_of_words] => 16722 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14514911 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/514911
Linking circuitry selectively coupling TDI/TDO with first and second domains Oct 14, 2014 Issued
Array ( [id] => 10136981 [patent_doc_number] => 09170299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-27 [patent_title] => 'DDR addressable TAP interface with shadow protocol and TAP domain' [patent_app_type] => utility [patent_app_number] => 14/508526 [patent_app_country] => US [patent_app_date] => 2014-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 34 [patent_no_of_words] => 9626 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14508526 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/508526
DDR addressable TAP interface with shadow protocol and TAP domain Oct 6, 2014 Issued
Array ( [id] => 10535933 [patent_doc_number] => 09261558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-16 [patent_title] => 'Interposer monitor coupled to clock, start, enable of monitor trigger' [patent_app_type] => utility [patent_app_number] => 14/505948 [patent_app_country] => US [patent_app_date] => 2014-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 50 [patent_no_of_words] => 11481 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14505948 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/505948
Interposer monitor coupled to clock, start, enable of monitor trigger Oct 2, 2014 Issued
Menu