Search

Cynthia H. Britt

Examiner (ID: 11869)

Most Active Art Unit
2117
Art Unit(s)
2117, 2111, 2133, 2138
Total Applications
1844
Issued Applications
1687
Pending Applications
80
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10557636 [patent_doc_number] => 09281845 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-08 [patent_title] => 'Layered redundancy encoding schemes for data storage' [patent_app_type] => utility [patent_app_number] => 14/503221 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9286 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14503221 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/503221
Layered redundancy encoding schemes for data storage Sep 29, 2014 Issued
Array ( [id] => 10687426 [patent_doc_number] => 20160033571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'LOGIC-BUILT-IN-SELF-TEST DIAGNOSTIC METHOD FOR ROOT CAUSE IDENTIFICATION' [patent_app_type] => utility [patent_app_number] => 14/502455 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3329 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14502455 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/502455
Logic-built-in-self-test diagnostic method for root cause identification Sep 29, 2014 Issued
Array ( [id] => 9800845 [patent_doc_number] => 20150012789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-08 [patent_title] => 'OPTIMIZED JTAG INTERFACE' [patent_app_type] => utility [patent_app_number] => 14/494787 [patent_app_country] => US [patent_app_date] => 2014-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 14824 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14494787 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/494787
Operating state machine from reset to poll in to reset Sep 23, 2014 Issued
Array ( [id] => 12453897 [patent_doc_number] => 09983830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-29 [patent_title] => Memory component having internal read modify-write operation [patent_app_type] => utility [patent_app_number] => 15/022176 [patent_app_country] => US [patent_app_date] => 2014-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8469 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15022176 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/022176
Memory component having internal read modify-write operation Sep 22, 2014 Issued
Array ( [id] => 11855566 [patent_doc_number] => 20170230058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-10 [patent_title] => 'Encoding Method, Decoding Method, Encoding Device and Decoding Device for Structured LDPC' [patent_app_type] => utility [patent_app_number] => 15/120126 [patent_app_country] => US [patent_app_date] => 2014-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 12748 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15120126 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/120126
Encoding method, decoding method, encoding device and decoding device for structured LDPC Aug 24, 2014 Issued
Array ( [id] => 10948644 [patent_doc_number] => 20140351665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-27 [patent_title] => 'INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES' [patent_app_type] => utility [patent_app_number] => 14/456125 [patent_app_country] => US [patent_app_date] => 2014-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6181 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14456125 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/456125
Interface circuitry with JTAG interface, full and reduced pin interfaces Aug 10, 2014 Issued
Array ( [id] => 10041800 [patent_doc_number] => 09082512 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-07-14 [patent_title] => 'Die-level monitoring in a storage cluster' [patent_app_type] => utility [patent_app_number] => 14/454522 [patent_app_country] => US [patent_app_date] => 2014-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14454522 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/454522
Die-level monitoring in a storage cluster Aug 6, 2014 Issued
Array ( [id] => 10392785 [patent_doc_number] => 20150277793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'MEMORY SYSTEM AND METHOD OF CONTROLLING MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/452930 [patent_app_country] => US [patent_app_date] => 2014-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4071 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14452930 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/452930
Memory system and method of controlling memory system Aug 5, 2014 Issued
Array ( [id] => 10941503 [patent_doc_number] => 20140344524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-20 [patent_title] => 'ADAPTIVE OVER-PROVISIONING IN MEMORY SYSTEMS' [patent_app_type] => utility [patent_app_number] => 14/451687 [patent_app_country] => US [patent_app_date] => 2014-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11389 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14451687 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/451687
Adaptive over-provisioning in memory systems Aug 4, 2014 Issued
Array ( [id] => 10948632 [patent_doc_number] => 20140351653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-27 [patent_title] => 'MEMORY CARD TEST INTERFACE' [patent_app_type] => utility [patent_app_number] => 14/452391 [patent_app_country] => US [patent_app_date] => 2014-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7643 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14452391 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/452391
Memory card test interface Aug 4, 2014 Issued
Array ( [id] => 9814588 [patent_doc_number] => 20150026533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-22 [patent_title] => 'WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE' [patent_app_type] => utility [patent_app_number] => 14/446873 [patent_app_country] => US [patent_app_date] => 2014-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4661 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14446873 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/446873
First/second die, channel interfaces, TAPs, and TLMs with common clock Jul 29, 2014 Issued
Array ( [id] => 10687425 [patent_doc_number] => 20160033570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'LOGIC-BUILT-IN-SELF-TEST DIAGNOSTIC METHOD FOR ROOT CAUSE IDENTIFICATION' [patent_app_type] => utility [patent_app_number] => 14/446516 [patent_app_country] => US [patent_app_date] => 2014-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3118 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14446516 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/446516
Logic-built-in-self-test diagnostic method for root cause identification Jul 29, 2014 Issued
Array ( [id] => 11278762 [patent_doc_number] => 09495242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-15 [patent_title] => 'Adaptive error correction in a memory system' [patent_app_type] => utility [patent_app_number] => 14/446922 [patent_app_country] => US [patent_app_date] => 2014-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6640 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14446922 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/446922
Adaptive error correction in a memory system Jul 29, 2014 Issued
Array ( [id] => 9912239 [patent_doc_number] => 20150067442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'INFORMATION PROCESSING APPARATUS AND DATA REPAIRING METHOD' [patent_app_type] => utility [patent_app_number] => 14/338646 [patent_app_country] => US [patent_app_date] => 2014-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13476 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14338646 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/338646
Information processing apparatus and data repairing method Jul 22, 2014 Issued
Array ( [id] => 10536617 [patent_doc_number] => 09262247 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-16 [patent_title] => 'Updating data stored in a dispersed storage network' [patent_app_type] => utility [patent_app_number] => 14/331596 [patent_app_country] => US [patent_app_date] => 2014-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 30 [patent_no_of_words] => 27344 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14331596 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/331596
Updating data stored in a dispersed storage network Jul 14, 2014 Issued
Array ( [id] => 10046619 [patent_doc_number] => 09087016 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-21 [patent_title] => 'Detecting intentional corruption of data in a dispersed storage network' [patent_app_type] => utility [patent_app_number] => 14/330194 [patent_app_country] => US [patent_app_date] => 2014-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 28 [patent_no_of_words] => 28512 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14330194 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/330194
Detecting intentional corruption of data in a dispersed storage network Jul 13, 2014 Issued
Array ( [id] => 10914441 [patent_doc_number] => 20140317460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-23 [patent_title] => 'MEMORY DEVICE WITH BACKGROUND BUILT-IN SELF-REPAIR USING BACKGROUND BUILT-IN SELF-TESTING' [patent_app_type] => utility [patent_app_number] => 14/320632 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 20836 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14320632 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/320632
Memory device with background built-in self-repair using background built-in self-testing Jun 29, 2014 Issued
Array ( [id] => 11194135 [patent_doc_number] => 09424953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-23 [patent_title] => 'Semiconductor memory device including repair circuit' [patent_app_type] => utility [patent_app_number] => 14/310405 [patent_app_country] => US [patent_app_date] => 2014-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 28315 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14310405 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/310405
Semiconductor memory device including repair circuit Jun 19, 2014 Issued
Array ( [id] => 11788202 [patent_doc_number] => 09397698 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-07-19 [patent_title] => 'Methods and apparatus for error recovery in memory systems employing iterative codes' [patent_app_type] => utility [patent_app_number] => 14/310673 [patent_app_country] => US [patent_app_date] => 2014-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9042 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14310673 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/310673
Methods and apparatus for error recovery in memory systems employing iterative codes Jun 19, 2014 Issued
Array ( [id] => 10645134 [patent_doc_number] => 09362007 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-07 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 14/310326 [patent_app_country] => US [patent_app_date] => 2014-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 25196 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14310326 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/310326
Semiconductor memory device Jun 19, 2014 Issued
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