Search

Cynthia H. Britt

Examiner (ID: 11869)

Most Active Art Unit
2117
Art Unit(s)
2117, 2111, 2133, 2138
Total Applications
1844
Issued Applications
1687
Pending Applications
80
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20118805 [patent_doc_number] => 12368528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Optical transmitter with encoder encoding processed data including concatenating parity bits to generate fec data blocks [patent_app_type] => utility [patent_app_number] => 18/384267 [patent_app_country] => US [patent_app_date] => 2023-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 1358 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18384267 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/384267
Optical transmitter with encoder encoding processed data including concatenating parity bits to generate fec data blocks Oct 25, 2023 Issued
Array ( [id] => 18976137 [patent_doc_number] => 20240056229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => SHORT LATENCY FAST RETRANSMISSION TRIGGERING [patent_app_type] => utility [patent_app_number] => 18/491612 [patent_app_country] => US [patent_app_date] => 2023-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15104 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18491612 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/491612
Short latency fast retransmission triggering Oct 19, 2023 Issued
Array ( [id] => 19099609 [patent_doc_number] => 20240118837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => MEMORY COMPONENT HAVING INTERNAL READ-MODIFY-WRITE OPERATION [patent_app_type] => utility [patent_app_number] => 18/487955 [patent_app_country] => US [patent_app_date] => 2023-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8587 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18487955 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/487955
Memory component having internal read-modify-write operation Oct 15, 2023 Issued
Array ( [id] => 19302180 [patent_doc_number] => 20240230757 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => Test device for testing on-chip clock controller having debug function [patent_app_type] => utility [patent_app_number] => 18/379686 [patent_app_country] => US [patent_app_date] => 2023-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5437 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18379686 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/379686
Test device for testing on-chip clock controller having debug function Oct 12, 2023 Issued
Array ( [id] => 19302180 [patent_doc_number] => 20240230757 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => Test device for testing on-chip clock controller having debug function [patent_app_type] => utility [patent_app_number] => 18/379686 [patent_app_country] => US [patent_app_date] => 2023-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5437 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18379686 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/379686
Test device for testing on-chip clock controller having debug function Oct 12, 2023 Issued
Array ( [id] => 19863784 [patent_doc_number] => 20250102570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => TESTING MULTI-CYCLE PATHS BASED ON CLOCK PATTERN [patent_app_type] => utility [patent_app_number] => 18/475047 [patent_app_country] => US [patent_app_date] => 2023-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8223 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18475047 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/475047
Testing multi-cycle paths based on clock pattern Sep 25, 2023 Issued
Array ( [id] => 19863784 [patent_doc_number] => 20250102570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => TESTING MULTI-CYCLE PATHS BASED ON CLOCK PATTERN [patent_app_type] => utility [patent_app_number] => 18/475047 [patent_app_country] => US [patent_app_date] => 2023-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8223 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18475047 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/475047
Testing multi-cycle paths based on clock pattern Sep 25, 2023 Issued
Array ( [id] => 18917665 [patent_doc_number] => 11879941 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-01-23 [patent_title] => Scan testing using scan frames with embedded commands [patent_app_type] => utility [patent_app_number] => 18/372784 [patent_app_country] => US [patent_app_date] => 2023-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 31 [patent_no_of_words] => 9706 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18372784 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/372784
Scan testing using scan frames with embedded commands Sep 25, 2023 Issued
Array ( [id] => 19068648 [patent_doc_number] => 20240103074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => Functional Circuit Block Harvesting in Computer Systems [patent_app_type] => utility [patent_app_number] => 18/471096 [patent_app_country] => US [patent_app_date] => 2023-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18471096 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/471096
Functional circuit block harvesting in computer systems Sep 19, 2023 Issued
Array ( [id] => 19068648 [patent_doc_number] => 20240103074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => Functional Circuit Block Harvesting in Computer Systems [patent_app_type] => utility [patent_app_number] => 18/471096 [patent_app_country] => US [patent_app_date] => 2023-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18471096 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/471096
Functional circuit block harvesting in computer systems Sep 19, 2023 Issued
Array ( [id] => 19481090 [patent_doc_number] => 20240329132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT AND TEST METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/244162 [patent_app_country] => US [patent_app_date] => 2023-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18244162 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/244162
Semiconductor integrated circuit and test method for semiconductor integrated circuit Sep 7, 2023 Issued
Array ( [id] => 19779972 [patent_doc_number] => 12229005 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Memory system and nonvolatile memory [patent_app_type] => utility [patent_app_number] => 18/463535 [patent_app_country] => US [patent_app_date] => 2023-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 34328 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18463535 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/463535
Memory system and nonvolatile memory Sep 7, 2023 Issued
Array ( [id] => 19927053 [patent_doc_number] => 12301354 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => System architecture of network coding at user plane function [patent_app_type] => utility [patent_app_number] => 18/458966 [patent_app_country] => US [patent_app_date] => 2023-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 18233 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18458966 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/458966
System architecture of network coding at user plane function Aug 29, 2023 Issued
Array ( [id] => 19161919 [patent_doc_number] => 20240154626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => NEURAL-NETWORK-OPTIMIZED DEGREE-SPECIFIC WEIGHTS FOR LDPC MINSUM DECODING [patent_app_type] => utility [patent_app_number] => 18/240162 [patent_app_country] => US [patent_app_date] => 2023-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8892 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18240162 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/240162
NEURAL-NETWORK-OPTIMIZED DEGREE-SPECIFIC WEIGHTS FOR LDPC MINSUM DECODING Aug 29, 2023 Pending
Array ( [id] => 18849903 [patent_doc_number] => 20230412307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => ERROR RECOVERY AND POWER MANAGEMENT BETWEEN NODES OF AN INTERCONNECTION NETWORK [patent_app_type] => utility [patent_app_number] => 18/240143 [patent_app_country] => US [patent_app_date] => 2023-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18240143 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/240143
Error recovery and power management between nodes of an interconnection network Aug 29, 2023 Issued
Array ( [id] => 19764104 [patent_doc_number] => 12222390 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Fault tolerant synchronizer [patent_app_type] => utility [patent_app_number] => 18/457537 [patent_app_country] => US [patent_app_date] => 2023-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3643 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18457537 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/457537
Fault tolerant synchronizer Aug 28, 2023 Issued
Array ( [id] => 18831986 [patent_doc_number] => 20230400513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => ADDRESSABLE TEST ACCESS PORT [patent_app_type] => utility [patent_app_number] => 18/237573 [patent_app_country] => US [patent_app_date] => 2023-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16325 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18237573 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/237573
Addressable test access port Aug 23, 2023 Issued
Array ( [id] => 20344244 [patent_doc_number] => 12467971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Scan testing using scan frames with embedded commands [patent_app_type] => utility [patent_app_number] => 18/234003 [patent_app_country] => US [patent_app_date] => 2023-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 31 [patent_no_of_words] => 4784 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18234003 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/234003
Scan testing using scan frames with embedded commands Aug 14, 2023 Issued
Array ( [id] => 20344244 [patent_doc_number] => 12467971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Scan testing using scan frames with embedded commands [patent_app_type] => utility [patent_app_number] => 18/234003 [patent_app_country] => US [patent_app_date] => 2023-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 31 [patent_no_of_words] => 4784 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18234003 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/234003
Scan testing using scan frames with embedded commands Aug 14, 2023 Issued
Array ( [id] => 19741830 [patent_doc_number] => 12218683 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-02-04 [patent_title] => Log likelihood ratios adjustment based on error tracker [patent_app_type] => utility [patent_app_number] => 18/447969 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9565 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447969 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/447969
Log likelihood ratios adjustment based on error tracker Aug 9, 2023 Issued
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