
Cynthia H. Britt
Examiner (ID: 11869)
| Most Active Art Unit | 2117 |
| Art Unit(s) | 2117, 2111, 2133, 2138 |
| Total Applications | 1844 |
| Issued Applications | 1687 |
| Pending Applications | 80 |
| Abandoned Applications | 105 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9083286
[patent_doc_number] => 20130268816
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-10
[patent_title] => 'Interconnections for Plural and Hierarchical P1500 Test Wrappers'
[patent_app_type] => utility
[patent_app_number] => 13/909416
[patent_app_country] => US
[patent_app_date] => 2013-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 9217
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13909416
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/909416 | Enable gating clock, shift, capture, and update to first gating | Jun 3, 2013 | Issued |
Array
(
[id] => 9096515
[patent_doc_number] => 20130275826
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-17
[patent_title] => 'Interconnections for Plural and Hierarchical P1500 Test Wrappers'
[patent_app_type] => utility
[patent_app_number] => 13/909399
[patent_app_country] => US
[patent_app_date] => 2013-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 9217
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13909399
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/909399 | Enable gating select signal to P1500 IR and DR gating | Jun 3, 2013 | Issued |
Array
(
[id] => 9980544
[patent_doc_number] => 09026875
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-05-05
[patent_title] => 'Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test'
[patent_app_type] => utility
[patent_app_number] => 13/894670
[patent_app_country] => US
[patent_app_date] => 2013-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 28
[patent_no_of_words] => 15358
[patent_no_of_claims] => 55
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 269
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13894670
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/894670 | Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test | May 14, 2013 | Issued |
Array
(
[id] => 9044235
[patent_doc_number] => 20130246873
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-09-19
[patent_title] => 'SELECTIVELY ACCESSING TEST ACCESS PORTS IN A MULTIPLE TEST ACCESS PORT ENVIRONMENT'
[patent_app_type] => utility
[patent_app_number] => 13/894089
[patent_app_country] => US
[patent_app_date] => 2013-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7522
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13894089
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/894089 | Tap instruction register with four bits for TLM selection | May 13, 2013 | Issued |
Array
(
[id] => 9967916
[patent_doc_number] => 09015552
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-04-21
[patent_title] => 'Data deduplication using CRC-seed differentiation between data and stubs'
[patent_app_type] => utility
[patent_app_number] => 13/894016
[patent_app_country] => US
[patent_app_date] => 2013-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 4492
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13894016
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/894016 | Data deduplication using CRC-seed differentiation between data and stubs | May 13, 2013 | Issued |
Array
(
[id] => 9056894
[patent_doc_number] => 20130254608
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-09-26
[patent_title] => 'IEEE 1149.1 AND P1500 TEST INTERFACES COMBINED CIRCUITS AND PROCESSES'
[patent_app_type] => utility
[patent_app_number] => 13/894157
[patent_app_country] => US
[patent_app_date] => 2013-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 60
[patent_figures_cnt] => 60
[patent_no_of_words] => 19840
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13894157
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/894157 | TAP/WRAPPER circuit blocks having two data register control gating circuits | May 13, 2013 | Issued |
Array
(
[id] => 9056896
[patent_doc_number] => 20130254610
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-09-26
[patent_title] => 'Interconnections for Plural and Hierarchical P1500 Test Wrappers'
[patent_app_type] => utility
[patent_app_number] => 13/892473
[patent_app_country] => US
[patent_app_date] => 2013-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 9190
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13892473
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/892473 | Input, output, and link instruction circuits for hierarchical P1500 wrappers | May 12, 2013 | Issued |
Array
(
[id] => 9257856
[patent_doc_number] => 08621297
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-12-31
[patent_title] => 'Scan path switches selectively connecting input buffer and test leads'
[patent_app_type] => utility
[patent_app_number] => 13/891885
[patent_app_country] => US
[patent_app_date] => 2013-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 47
[patent_no_of_words] => 18194
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13891885
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/891885 | Scan path switches selectively connecting input buffer and test leads | May 9, 2013 | Issued |
Array
(
[id] => 9056892
[patent_doc_number] => 20130254606
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-09-26
[patent_title] => 'METHOD AND APPARATUS FOR DEVICE ACCESS PORT SELECTION'
[patent_app_type] => utility
[patent_app_number] => 13/891840
[patent_app_country] => US
[patent_app_date] => 2013-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 17805
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13891840
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/891840 | Access port selector for access port and compliant access port | May 9, 2013 | Issued |
Array
(
[id] => 9123879
[patent_doc_number] => 20130290801
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-31
[patent_title] => 'SCAN RESPONSE REUSE METHOD AND APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 13/890781
[patent_app_country] => US
[patent_app_date] => 2013-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 33
[patent_no_of_words] => 9401
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13890781
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/890781 | Formatter selectively routing response data to stimulus data inputs | May 8, 2013 | Issued |
Array
(
[id] => 9891645
[patent_doc_number] => 08977920
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-03-10
[patent_title] => 'DDR circuitry data and control buses connected to test circuitry'
[patent_app_type] => utility
[patent_app_number] => 13/889004
[patent_app_country] => US
[patent_app_date] => 2013-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 49
[patent_figures_cnt] => 63
[patent_no_of_words] => 24037
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13889004
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/889004 | DDR circuitry data and control buses connected to test circuitry | May 6, 2013 | Issued |
Array
(
[id] => 9056891
[patent_doc_number] => 20130254605
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-09-26
[patent_title] => 'HIGH SPEED DOUBLE DATA RATE JTAG INTERFACE'
[patent_app_type] => utility
[patent_app_number] => 13/887862
[patent_app_country] => US
[patent_app_date] => 2013-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 9605
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13887862
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/887862 | DDR JTAG interface setting flip-flops in high state at power-up | May 5, 2013 | Issued |
Array
(
[id] => 9044233
[patent_doc_number] => 20130246871
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-09-19
[patent_title] => 'ADAPTING SCAN-BIST ARCHITECTURES FOR LOW POWER OPERATION'
[patent_app_type] => utility
[patent_app_number] => 13/870272
[patent_app_country] => US
[patent_app_date] => 2013-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 9447
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13870272
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/870272 | Generator and compactor adaptor for low power divided scan path | Apr 24, 2013 | Issued |
Array
(
[id] => 9500148
[patent_doc_number] => 08738989
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-05-27
[patent_title] => 'Method and apparatus for detecting free page and a method and apparatus for decoding error correction code using the method and apparatus for detecting free page'
[patent_app_type] => utility
[patent_app_number] => 13/859976
[patent_app_country] => US
[patent_app_date] => 2013-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 3963
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13859976
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/859976 | Method and apparatus for detecting free page and a method and apparatus for decoding error correction code using the method and apparatus for detecting free page | Apr 9, 2013 | Issued |
Array
(
[id] => 9926371
[patent_doc_number] => 08984357
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-03-17
[patent_title] => 'Wrapper selector data register having control outputs and SELECTAM input'
[patent_app_type] => utility
[patent_app_number] => 13/858608
[patent_app_country] => US
[patent_app_date] => 2013-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
[patent_figures_cnt] => 56
[patent_no_of_words] => 20874
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13858608
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/858608 | Wrapper selector data register having control outputs and SELECTAM input | Apr 7, 2013 | Issued |
Array
(
[id] => 9006238
[patent_doc_number] => 20130227363
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-08-29
[patent_title] => 'OPTIMIZED JTAG INTERFACE'
[patent_app_type] => utility
[patent_app_number] => 13/855970
[patent_app_country] => US
[patent_app_date] => 2013-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 14766
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13855970
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/855970 | Transitioning POLL IN to set MRST and CE high states | Apr 2, 2013 | Issued |
Array
(
[id] => 11818668
[patent_doc_number] => 09722637
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-08-01
[patent_title] => 'Construction of MBR (minimum bandwidth regenerating) codes and a method to repair the storage nodes'
[patent_app_type] => utility
[patent_app_number] => 13/996825
[patent_app_country] => US
[patent_app_date] => 2013-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 10074
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 566
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13996825
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/996825 | Construction of MBR (minimum bandwidth regenerating) codes and a method to repair the storage nodes | Mar 25, 2013 | Issued |
Array
(
[id] => 8918118
[patent_doc_number] => 20130179744
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-07-11
[patent_title] => 'DIRECT SCAN ACCESS JTAG'
[patent_app_type] => utility
[patent_app_number] => 13/782585
[patent_app_country] => US
[patent_app_date] => 2013-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 14081
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13782585
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/782585 | JTAG multiplexer with clock/mode input, mode/clock input, and clock output | Feb 28, 2013 | Issued |
Array
(
[id] => 9891665
[patent_doc_number] => 08977940
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-03-10
[patent_title] => 'Error event processing methods and systems'
[patent_app_type] => utility
[patent_app_number] => 13/776848
[patent_app_country] => US
[patent_app_date] => 2013-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7671
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13776848
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/776848 | Error event processing methods and systems | Feb 25, 2013 | Issued |
Array
(
[id] => 8893794
[patent_doc_number] => 20130166978
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-06-27
[patent_title] => 'INTEGRATED CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 13/770329
[patent_app_country] => US
[patent_app_date] => 2013-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 11223
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13770329
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/770329 | INTEGRATED CIRCUIT | Feb 18, 2013 | Abandoned |