Search

Cynthia H. Britt

Examiner (ID: 11869)

Most Active Art Unit
2117
Art Unit(s)
2117, 2111, 2133, 2138
Total Applications
1844
Issued Applications
1687
Pending Applications
80
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9891644 [patent_doc_number] => 08977919 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-10 [patent_title] => 'Scan, test, and control circuits coupled to IC surfaces contacts' [patent_app_type] => utility [patent_app_number] => 13/765260 [patent_app_country] => US [patent_app_date] => 2013-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 24 [patent_no_of_words] => 4978 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13765260 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/765260
Scan, test, and control circuits coupled to IC surfaces contacts Feb 11, 2013 Issued
Array ( [id] => 8868213 [patent_doc_number] => 20130151916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFF-CHIP TAP INTERFACE PORT' [patent_app_type] => utility [patent_app_number] => 13/765194 [patent_app_country] => US [patent_app_date] => 2013-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5975 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13765194 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/765194
Separate dies with interfaces and selection circuitry connected by leads Feb 11, 2013 Issued
Array ( [id] => 9187161 [patent_doc_number] => 08627161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-07 [patent_title] => 'Low power divided scan paths with adapter and scan controller' [patent_app_type] => utility [patent_app_number] => 13/757305 [patent_app_country] => US [patent_app_date] => 2013-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 13475 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 363 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13757305 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/757305
Low power divided scan paths with adapter and scan controller Jan 31, 2013 Issued
Array ( [id] => 9029694 [patent_doc_number] => 08539291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-17 [patent_title] => 'Circuits with selectable paths of control and data scan cells' [patent_app_type] => utility [patent_app_number] => 13/757334 [patent_app_country] => US [patent_app_date] => 2013-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4703 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 667 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13757334 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/757334
Circuits with selectable paths of control and data scan cells Jan 31, 2013 Issued
Array ( [id] => 9826097 [patent_doc_number] => 08935593 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-01-13 [patent_title] => 'Method and apparatus for flexible buffers in an XOR engine' [patent_app_type] => utility [patent_app_number] => 13/748078 [patent_app_country] => US [patent_app_date] => 2013-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4322 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13748078 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/748078
Method and apparatus for flexible buffers in an XOR engine Jan 22, 2013 Issued
Array ( [id] => 9853065 [patent_doc_number] => 08954814 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-10 [patent_title] => 'Method and apparatus for decoding' [patent_app_type] => utility [patent_app_number] => 13/745466 [patent_app_country] => US [patent_app_date] => 2013-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 8407 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13745466 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/745466
Method and apparatus for decoding Jan 17, 2013 Issued
Array ( [id] => 9871611 [patent_doc_number] => 08959404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-17 [patent_title] => 'Method for controlling access operations of a flash memory, and associated flash memory device and flash memory controller' [patent_app_type] => utility [patent_app_number] => 13/741396 [patent_app_country] => US [patent_app_date] => 2013-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3138 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13741396 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/741396
Method for controlling access operations of a flash memory, and associated flash memory device and flash memory controller Jan 14, 2013 Issued
Array ( [id] => 8823891 [patent_doc_number] => 20130124935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'REDUCED SIGNALING INTERFACE METHOD & APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/735545 [patent_app_country] => US [patent_app_date] => 2013-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 21217 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13735545 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/735545
IC with addressable test access port domain selection circuitry Jan 6, 2013 Issued
Array ( [id] => 8827735 [patent_doc_number] => 20130128780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'USER EQUIPMENT USING HYBRID AUTOMATIC REPEAT REQUEST' [patent_app_type] => utility [patent_app_number] => 13/722798 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2697 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13722798 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/722798
User equipment using hybrid automatic repeat request Dec 19, 2012 Issued
Array ( [id] => 8790968 [patent_doc_number] => 20130107937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-02 [patent_title] => 'Method and Apparatus for Deinterleaving in a Digital Communication System' [patent_app_type] => utility [patent_app_number] => 13/720899 [patent_app_country] => US [patent_app_date] => 2012-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 17765 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13720899 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/720899
Method and Apparatus for Deinterleaving in a Digital Communication System Dec 18, 2012 Abandoned
Array ( [id] => 8769429 [patent_doc_number] => 20130097466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-18 [patent_title] => 'REMOVABLE AND REPLACEABLE TAP DOMAIN SELECTION CIRCUITRY' [patent_app_type] => utility [patent_app_number] => 13/693593 [patent_app_country] => US [patent_app_date] => 2012-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9874 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13693593 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/693593
Tap domain selection circuitry with multiplexer and control circuitry Dec 3, 2012 Issued
Array ( [id] => 9879056 [patent_doc_number] => 08966352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'Memory controller supporting rate-compatible punctured codes and supporting block codes' [patent_app_type] => utility [patent_app_number] => 13/680908 [patent_app_country] => US [patent_app_date] => 2012-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5144 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13680908 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/680908
Memory controller supporting rate-compatible punctured codes and supporting block codes Nov 18, 2012 Issued
Array ( [id] => 8722700 [patent_doc_number] => 20130073917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-21 [patent_title] => 'DOUBLE DATA RATE TEST INTERFACE AND ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 13/678899 [patent_app_country] => US [patent_app_date] => 2012-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 50 [patent_no_of_words] => 24010 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13678899 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/678899
IC with wrapper, TAM, TAM controller, and DDR circuitry Nov 15, 2012 Issued
Array ( [id] => 9012502 [patent_doc_number] => 08527823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-03 [patent_title] => 'Gating of clock-DR and pause-DR from TAP to TCA' [patent_app_type] => utility [patent_app_number] => 13/676344 [patent_app_country] => US [patent_app_date] => 2012-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 51 [patent_no_of_words] => 14761 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13676344 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/676344
Gating of clock-DR and pause-DR from TAP to TCA Nov 13, 2012 Issued
Array ( [id] => 8878810 [patent_doc_number] => 08473794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-25 [patent_title] => 'First, update, and second TDI and TMS flip-flop TAP circuitry' [patent_app_type] => utility [patent_app_number] => 13/671751 [patent_app_country] => US [patent_app_date] => 2012-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 34 [patent_no_of_words] => 9588 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13671751 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/671751
First, update, and second TDI and TMS flip-flop TAP circuitry Nov 7, 2012 Issued
Array ( [id] => 8843389 [patent_doc_number] => 20130139017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-30 [patent_title] => '1149.1 TAP LINKING MODULES' [patent_app_type] => utility [patent_app_number] => 13/670078 [patent_app_country] => US [patent_app_date] => 2012-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4374 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13670078 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/670078
Output linking circuitry for multiple TAP domains Nov 5, 2012 Issued
Array ( [id] => 9879042 [patent_doc_number] => 08966338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'Cyclic redundancy check code generating circuit, semiconductor memory device, and method of driving semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/666560 [patent_app_country] => US [patent_app_date] => 2012-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 8671 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13666560 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/666560
Cyclic redundancy check code generating circuit, semiconductor memory device, and method of driving semiconductor memory device Oct 31, 2012 Issued
Array ( [id] => 9444251 [patent_doc_number] => 08713387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-29 [patent_title] => 'Channel marking for chip mark overflow and calibration errors' [patent_app_type] => utility [patent_app_number] => 13/658148 [patent_app_country] => US [patent_app_date] => 2012-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7109 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13658148 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/658148
Channel marking for chip mark overflow and calibration errors Oct 22, 2012 Issued
Array ( [id] => 8672511 [patent_doc_number] => 20130047048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-21 [patent_title] => 'AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL' [patent_app_type] => utility [patent_app_number] => 13/657082 [patent_app_country] => US [patent_app_date] => 2012-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 15560 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13657082 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/657082
Decode logic driving segmented scan cells with clocks and enables Oct 21, 2012 Issued
Array ( [id] => 8661331 [patent_doc_number] => 20130042160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-14 [patent_title] => 'SERIAL I/O USING JTAG TCK AND TMS SIGNALS' [patent_app_type] => utility [patent_app_number] => 13/653705 [patent_app_country] => US [patent_app_date] => 2012-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 14950 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13653705 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/653705
Data source, destination and input/output circuit with multiplexer and flip-flop Oct 16, 2012 Issued
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