Search

Cynthia H. Britt

Examiner (ID: 11869)

Most Active Art Unit
2117
Art Unit(s)
2117, 2111, 2133, 2138
Total Applications
1844
Issued Applications
1687
Pending Applications
80
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8661332 [patent_doc_number] => 20130042161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-14 [patent_title] => 'LOW POWER TESTING OF VERY LARGE CIRCUITS' [patent_app_type] => utility [patent_app_number] => 13/653716 [patent_app_country] => US [patent_app_date] => 2012-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4116 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13653716 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/653716
State machine transitioning between idle, capture, shift-I, and shift-2 states Oct 16, 2012 Issued
Array ( [id] => 9507121 [patent_doc_number] => 08745450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-03 [patent_title] => 'Fully-buffered dual in-line memory module with fault correction' [patent_app_type] => utility [patent_app_number] => 13/632547 [patent_app_country] => US [patent_app_date] => 2012-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 44 [patent_no_of_words] => 17459 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13632547 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/632547
Fully-buffered dual in-line memory module with fault correction Sep 30, 2012 Issued
Array ( [id] => 8619427 [patent_doc_number] => 20130024739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-24 [patent_title] => 'SELECTIVELY ACCESSING TEST ACCESS PORTS IN A MULTIPLE TEST ACCESS PORT ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 13/628834 [patent_app_country] => US [patent_app_date] => 2012-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7495 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13628834 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/628834
IC TAP with IR select output and controller enable input Sep 26, 2012 Issued
Array ( [id] => 10362894 [patent_doc_number] => 20150247899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-03 [patent_title] => 'SCAN TEST SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/431794 [patent_app_country] => US [patent_app_date] => 2012-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6627 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14431794 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/431794
Scan test system with a test interface having a clock control unit for stretching a power shift cycle Sep 26, 2012 Issued
Array ( [id] => 8873019 [patent_doc_number] => 08468406 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-18 [patent_title] => 'Access port selector and gating selecting test access port' [patent_app_type] => utility [patent_app_number] => 13/628802 [patent_app_country] => US [patent_app_date] => 2012-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 58 [patent_no_of_words] => 17789 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13628802 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/628802
Access port selector and gating selecting test access port Sep 26, 2012 Issued
Array ( [id] => 8998189 [patent_doc_number] => 08522095 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Tap with address, state monitor and gating circuitry' [patent_app_type] => utility [patent_app_number] => 13/614615 [patent_app_country] => US [patent_app_date] => 2012-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 43 [patent_no_of_words] => 10427 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13614615 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/614615
Tap with address, state monitor and gating circuitry Sep 12, 2012 Issued
Array ( [id] => 8952808 [patent_doc_number] => 20130198589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-01 [patent_title] => 'METHOD OF OPERATING MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE MEMORY CONTROLLER' [patent_app_type] => utility [patent_app_number] => 13/612074 [patent_app_country] => US [patent_app_date] => 2012-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9160 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13612074 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/612074
Method of operating memory controller and memory system including the memory controller Sep 11, 2012 Issued
Array ( [id] => 8746734 [patent_doc_number] => 20130086451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'Reproducing data utilizing a zero information gain function' [patent_app_type] => utility [patent_app_number] => 13/612043 [patent_app_country] => US [patent_app_date] => 2012-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 21317 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13612043 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/612043
Reproducing data utilizing a zero information gain function Sep 11, 2012 Issued
Array ( [id] => 9071191 [patent_doc_number] => 20130262947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'INFORMATION PROCESSING APPARATUS, AND METHOD OF CONTROLLING INFORMATION PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/612098 [patent_app_country] => US [patent_app_date] => 2012-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10602 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13612098 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/612098
Information processing apparatus, and method of controlling information processing apparatus Sep 11, 2012 Issued
Array ( [id] => 9365392 [patent_doc_number] => 20140075265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'Outputting Information of ECC Corrected Bits' [patent_app_type] => utility [patent_app_number] => 13/612433 [patent_app_country] => US [patent_app_date] => 2012-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6594 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13612433 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/612433
Outputting information of ECC corrected bits Sep 11, 2012 Issued
Array ( [id] => 9714478 [patent_doc_number] => 08839081 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Rate matching and de-rate matching on digital signal processors' [patent_app_type] => utility [patent_app_number] => 13/609034 [patent_app_country] => US [patent_app_date] => 2012-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4896 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13609034 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/609034
Rate matching and de-rate matching on digital signal processors Sep 9, 2012 Issued
Array ( [id] => 9130272 [patent_doc_number] => 08578229 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-11-05 [patent_title] => 'High-throughput pipelined and scalable architecture for a K-Best MIMO detector' [patent_app_type] => utility [patent_app_number] => 13/603783 [patent_app_country] => US [patent_app_date] => 2012-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 26 [patent_no_of_words] => 12945 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13603783 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/603783
High-throughput pipelined and scalable architecture for a K-Best MIMO detector Sep 4, 2012 Issued
Array ( [id] => 9023571 [patent_doc_number] => 08533569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-10 [patent_title] => 'Apparatus, system, and method for managing data using a data pipeline' [patent_app_type] => utility [patent_app_number] => 13/600077 [patent_app_country] => US [patent_app_date] => 2012-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 25662 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13600077 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/600077
Apparatus, system, and method for managing data using a data pipeline Aug 29, 2012 Issued
Array ( [id] => 8524898 [patent_doc_number] => 20120324306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-20 [patent_title] => 'ADDRESSABLE TEST ACCESS PORT METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/596889 [patent_app_country] => US [patent_app_date] => 2012-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 16429 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13596889 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/596889
TAP test clock control circuitry connected to device address port Aug 27, 2012 Issued
Array ( [id] => 8518043 [patent_doc_number] => 20120317451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-13 [patent_title] => 'PROBELESS TESTING OF PAD BUFFERS ON WAFER' [patent_app_type] => utility [patent_app_number] => 13/591347 [patent_app_country] => US [patent_app_date] => 2012-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 18648 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13591347 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/591347
Pad switch cells selectively coupling test leads to test pads Aug 21, 2012 Issued
Array ( [id] => 8588721 [patent_doc_number] => 20130007542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'PREEMPTIVE MEMORY REPAIR BASED ON MULTI-SYMBOL, MULTI-SCRUB CYCLE ANALYSIS' [patent_app_type] => utility [patent_app_number] => 13/590998 [patent_app_country] => US [patent_app_date] => 2012-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9051 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13590998 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/590998
Preemptive memory repair based on multi-symbol, multi-scrub cycle analysis Aug 20, 2012 Issued
Array ( [id] => 8518044 [patent_doc_number] => 20120317452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-13 [patent_title] => 'INTERCONNECTIONS FOR PLURAL AND HIERARCHICAL P1500 TEST WRAPPERS' [patent_app_type] => utility [patent_app_number] => 13/590380 [patent_app_country] => US [patent_app_date] => 2012-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9163 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13590380 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/590380
Wrapper selection circuits with selection and enable inputs Aug 20, 2012 Issued
Array ( [id] => 10901559 [patent_doc_number] => 08924802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-30 [patent_title] => 'IC TAP with dual port router and additional capture input' [patent_app_type] => utility [patent_app_number] => 13/587522 [patent_app_country] => US [patent_app_date] => 2012-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 31 [patent_no_of_words] => 6980 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13587522 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/587522
IC TAP with dual port router and additional capture input Aug 15, 2012 Issued
Array ( [id] => 9089455 [patent_doc_number] => 08560902 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-15 [patent_title] => 'Writing scheme for phase change material-content addressable memory' [patent_app_type] => utility [patent_app_number] => 13/587146 [patent_app_country] => US [patent_app_date] => 2012-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3246 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13587146 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/587146
Writing scheme for phase change material-content addressable memory Aug 15, 2012 Issued
Array ( [id] => 9089455 [patent_doc_number] => 08560902 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-15 [patent_title] => 'Writing scheme for phase change material-content addressable memory' [patent_app_type] => utility [patent_app_number] => 13/587146 [patent_app_country] => US [patent_app_date] => 2012-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3246 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13587146 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/587146
Writing scheme for phase change material-content addressable memory Aug 15, 2012 Issued
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