Search

Cynthia H. Britt

Examiner (ID: 11869)

Most Active Art Unit
2117
Art Unit(s)
2117, 2111, 2133, 2138
Total Applications
1844
Issued Applications
1687
Pending Applications
80
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10847777 [patent_doc_number] => 08874978 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-28 [patent_title] => 'Information processing apparatus, information processing system, controlling method for information processing apparatus and program' [patent_app_type] => utility [patent_app_number] => 13/416431 [patent_app_country] => US [patent_app_date] => 2012-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 20713 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13416431 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/416431
Information processing apparatus, information processing system, controlling method for information processing apparatus and program Mar 8, 2012 Issued
Array ( [id] => 8873016 [patent_doc_number] => 08468403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-18 [patent_title] => 'Data register control from TAP+ATC or discrete WSP signals' [patent_app_type] => utility [patent_app_number] => 13/411124 [patent_app_country] => US [patent_app_date] => 2012-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 119 [patent_no_of_words] => 19875 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13411124 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/411124
Data register control from TAP+ATC or discrete WSP signals Mar 1, 2012 Issued
Array ( [id] => 10890680 [patent_doc_number] => 08914693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-16 [patent_title] => 'Apparatus for JTAG-driven remote scanning' [patent_app_type] => utility [patent_app_number] => 13/397544 [patent_app_country] => US [patent_app_date] => 2012-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3706 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13397544 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/397544
Apparatus for JTAG-driven remote scanning Feb 14, 2012 Issued
Array ( [id] => 8230059 [patent_doc_number] => 20120144255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'REDUCED SIGNALING INTERFACE METHOD & APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/396017 [patent_app_country] => US [patent_app_date] => 2012-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 21191 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13396017 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/396017
Tap interface select circuit with AUX1/02-TMS and TMS/RCK-RCK leads Feb 13, 2012 Issued
Array ( [id] => 8230049 [patent_doc_number] => 20120144254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFF-CHIP TAP INTERFACE PORT' [patent_app_type] => utility [patent_app_number] => 13/370521 [patent_app_country] => US [patent_app_date] => 2012-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5948 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13370521 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/370521
Selecting on die test port and off die interface leads Feb 9, 2012 Issued
Array ( [id] => 8979014 [patent_doc_number] => 20130212444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-15 [patent_title] => 'METHODOLOGY FOR CORRELATED MEMORY FAIL ESTIMATIONS' [patent_app_type] => utility [patent_app_number] => 13/369633 [patent_app_country] => US [patent_app_date] => 2012-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5163 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13369633 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/369633
Methodology for correlated memory fail estimations Feb 8, 2012 Issued
Array ( [id] => 10841295 [patent_doc_number] => 08868995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'Multicast digital video lost packet recovery' [patent_app_type] => utility [patent_app_number] => 13/366493 [patent_app_country] => US [patent_app_date] => 2012-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6793 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13366493 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/366493
Multicast digital video lost packet recovery Feb 5, 2012 Issued
Array ( [id] => 9251903 [patent_doc_number] => 08615694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-24 [patent_title] => 'Interposer TAP boundary register coupling stacked die functional input/output data' [patent_app_type] => utility [patent_app_number] => 13/362717 [patent_app_country] => US [patent_app_date] => 2012-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 66 [patent_no_of_words] => 14442 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13362717 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/362717
Interposer TAP boundary register coupling stacked die functional input/output data Jan 30, 2012 Issued
Array ( [id] => 8546425 [patent_doc_number] => 08321728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-27 [patent_title] => 'TAP with serial I/O coupled to TCK' [patent_app_type] => utility [patent_app_number] => 13/357089 [patent_app_country] => US [patent_app_date] => 2012-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 28 [patent_no_of_words] => 14932 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13357089 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/357089
TAP with serial I/O coupled to TCK Jan 23, 2012 Issued
Array ( [id] => 8189321 [patent_doc_number] => 20120117434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'PROBELESS TESTING OF PAD BUFFERS ON WAFER' [patent_app_type] => utility [patent_app_number] => 13/352484 [patent_app_country] => US [patent_app_date] => 2012-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 18648 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20120117434.pdf [firstpage_image] =>[orig_patent_app_number] => 13352484 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/352484
Scan path switch testing of output buffer with ESD Jan 17, 2012 Issued
Array ( [id] => 9123873 [patent_doc_number] => 20130290795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'Test Scheduling With Pattern-Independent Test Access Mechanism' [patent_app_type] => utility [patent_app_number] => 13/980287 [patent_app_country] => US [patent_app_date] => 2012-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6995 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13980287 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/980287
Test scheduling with pattern-independent test access mechanism Jan 16, 2012 Issued
Array ( [id] => 8299494 [patent_doc_number] => 20120182047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-19 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT AND POWER-SUPPLY VOLTAGE ADAPTIVE CONTROL SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/349279 [patent_app_country] => US [patent_app_date] => 2012-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 13470 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13349279 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/349279
Semiconductor integrated circuit and power-supply voltage adaptive control system Jan 11, 2012 Issued
Array ( [id] => 8267469 [patent_doc_number] => 20120166894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'CIRCUIT AND METHOD FOR CORRECTING SKEW IN A PLURALITY OF COMMUNICATION CHANNELS FOR COMMUNICATING WITH A MEMORY DEVICE, MEMORY CONTROLLER, SYSTEM AND METHOD USING THE SAME, AND MEMORY TEST SYSTEM AND METHOD USING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/347000 [patent_app_country] => US [patent_app_date] => 2012-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 18245 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13347000 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/347000
CIRCUIT AND METHOD FOR CORRECTING SKEW IN A PLURALITY OF COMMUNICATION CHANNELS FOR COMMUNICATING WITH A MEMORY DEVICE, MEMORY CONTROLLER, SYSTEM AND METHOD USING THE SAME, AND MEMORY TEST SYSTEM AND METHOD USING THE SAME Jan 9, 2012 Abandoned
Array ( [id] => 8189322 [patent_doc_number] => 20120117435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'PARALLEL AND SERIAL ACCESS TO TEST COMPRESSION ARCHITECTURES' [patent_app_type] => utility [patent_app_number] => 13/343998 [patent_app_country] => US [patent_app_date] => 2012-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 13926 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20120117435.pdf [firstpage_image] =>[orig_patent_app_number] => 13343998 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/343998
Programmable test compression architecture with serial input register and multiplexer Jan 4, 2012 Issued
Array ( [id] => 10969783 [patent_doc_number] => 20140372816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-18 [patent_title] => 'ACCESSING DATA STORED IN A COMMAND/ADDRESS REGISTER DEVICE' [patent_app_type] => utility [patent_app_number] => 13/995477 [patent_app_country] => US [patent_app_date] => 2011-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13995477 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/995477
Accessing data stored in a command/address register device Dec 21, 2011 Issued
Array ( [id] => 8561883 [patent_doc_number] => 08335953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-18 [patent_title] => 'IR gating SC signals during TAP Clock-DR and Pause-DR states' [patent_app_type] => utility [patent_app_number] => 13/330788 [patent_app_country] => US [patent_app_date] => 2011-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 51 [patent_no_of_words] => 14733 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13330788 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/330788
IR gating SC signals during TAP Clock-DR and Pause-DR states Dec 19, 2011 Issued
Array ( [id] => 8558215 [patent_doc_number] => 08332700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-11 [patent_title] => 'Multiplexer input linking circuitry to IC and core TAP domains' [patent_app_type] => utility [patent_app_number] => 13/330178 [patent_app_country] => US [patent_app_date] => 2011-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 4345 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 383 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13330178 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/330178
Multiplexer input linking circuitry to IC and core TAP domains Dec 18, 2011 Issued
Array ( [id] => 8098029 [patent_doc_number] => 20120084613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-05 [patent_title] => 'SCAN RESPONSE REUSE METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/325740 [patent_app_country] => US [patent_app_date] => 2011-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 9331 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20120084613.pdf [firstpage_image] =>[orig_patent_app_number] => 13325740 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/325740
Multiplexer with serial and scan data inputs for scan path Dec 13, 2011 Issued
Array ( [id] => 8574819 [patent_doc_number] => 08341482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-25 [patent_title] => 'User equipment using hybrid automatic repeat request' [patent_app_type] => utility [patent_app_number] => 13/311148 [patent_app_country] => US [patent_app_date] => 2011-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 2677 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13311148 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/311148
User equipment using hybrid automatic repeat request Dec 4, 2011 Issued
Array ( [id] => 8849344 [patent_doc_number] => 08458544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-04 [patent_title] => 'Multiple-capture DFT system to reduce peak capture power during self-test or scan test' [patent_app_type] => utility [patent_app_number] => 13/309987 [patent_app_country] => US [patent_app_date] => 2011-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 15321 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13309987 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/309987
Multiple-capture DFT system to reduce peak capture power during self-test or scan test Dec 1, 2011 Issued
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