Cynthia H. Britt

Array ( [id] => 10092014 [patent_doc_number] => 09128840 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-08 [patent_title] => 'Methods for providing for correcting data and associated apparatus' [patent_app_type] => utility [patent_app_number] => 13/877277 [patent_app_country] => US [patent_app_date] => 2011-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 54 [patent_no_of_words] => 21026 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13877277 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7735899 [patent_doc_number] => 20120017129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-19 [patent_title] => 'HIGH SPEED DOUBLE DATA RATE JTAG INTERFACE' [patent_app_type] => utility [patent_app_number] => 13/241503 [patent_app_country] => US [patent_app_date] => 2011-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 9561 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20120017129.pdf [firstpage_image] =>[orig_patent_app_number] => 13241503 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7722077 [patent_doc_number] => 20120011412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-12 [patent_title] => 'ADDRESSABLE TEST ACCESS PORT METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/238736 [patent_app_country] => US [patent_app_date] => 2011-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 16410 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20120011412.pdf [firstpage_image] =>[orig_patent_app_number] => 13238736 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7722075 [patent_doc_number] => 20120011410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-12 [patent_title] => 'SCAN TEST METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/238674 [patent_app_country] => US [patent_app_date] => 2011-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 22150 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20120011410.pdf [firstpage_image] =>[orig_patent_app_number] => 13238674 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7714301 [patent_doc_number] => 20120005546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'INTERCONNECTIONS FOR PLURAL AND HIERARCHICAL P1500 TEST WRAPPERS' [patent_app_type] => utility [patent_app_number] => 13/234217 [patent_app_country] => US [patent_app_date] => 2011-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9133 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20120005546.pdf [firstpage_image] =>[orig_patent_app_number] => 13234217 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7671730 [patent_doc_number] => 20110320999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'DECOMPRESSORS FOR LOW POWER DECOMPRESSION OF TEST PATTERNS' [patent_app_type] => utility [patent_app_number] => 13/225240 [patent_app_country] => US [patent_app_date] => 2011-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 17700 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13225240 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8355078 [patent_doc_number] => 08250421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-21 [patent_title] => 'Clock controller for JTAG interface' [patent_app_type] => utility [patent_app_number] => 13/197000 [patent_app_country] => US [patent_app_date] => 2011-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 43 [patent_no_of_words] => 14724 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13197000 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9404780 [patent_doc_number] => 08694844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-08 [patent_title] => 'AT speed TAP with dual port router and command circuit' [patent_app_type] => utility [patent_app_number] => 13/188078 [patent_app_country] => US [patent_app_date] => 2011-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 43 [patent_no_of_words] => 13087 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13188078 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7746970 [patent_doc_number] => 20120023387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-26 [patent_title] => 'CONTROLLING METHODS AND CONTROLLERS UTILIZED IN FLASH MEMORY DEVICE FOR REFERRING TO DATA COMPRESSION RESULT TO ADJUST ECC PROTECTION CAPABILITY' [patent_app_type] => utility [patent_app_number] => 13/187499 [patent_app_country] => US [patent_app_date] => 2011-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5382 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20120023387.pdf [firstpage_image] =>[orig_patent_app_number] => 13187499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9680600 [patent_doc_number] => 08819527 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-26 [patent_title] => 'Systems and methods for mitigating stubborn errors in a data processing system' [patent_app_type] => utility [patent_app_number] => 13/186234 [patent_app_country] => US [patent_app_date] => 2011-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6379 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13186234 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9486581 [patent_doc_number] => 08732543 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-20 [patent_title] => 'Tensor product codes for flash' [patent_app_type] => utility [patent_app_number] => 13/184949 [patent_app_country] => US [patent_app_date] => 2011-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6154 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13184949 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7588643 [patent_doc_number] => 20110283154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-17 [patent_title] => 'ADAPTING SCAN-BIST ARCHITECTURES FOR LOW POWER OPERATION' [patent_app_type] => utility [patent_app_number] => 13/184077 [patent_app_country] => US [patent_app_date] => 2011-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9403 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20110283154.pdf [firstpage_image] =>[orig_patent_app_number] => 13184077 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9257861 [patent_doc_number] => 08621302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-31 [patent_title] => 'Data summing boundary—cell connected with output and scan chain' [patent_app_type] => utility [patent_app_number] => 13/184045 [patent_app_country] => US [patent_app_date] => 2011-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 34 [patent_no_of_words] => 13568 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13184045 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7563013 [patent_doc_number] => 20110276847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-10 [patent_title] => 'SHADOW ACCESS PORT METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/183113 [patent_app_country] => US [patent_app_date] => 2011-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12999 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20110276847.pdf [firstpage_image] =>[orig_patent_app_number] => 13183113 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9102772 [patent_doc_number] => 08566666 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-22 [patent_title] => 'Min-sum based non-binary LDPC decoder' [patent_app_type] => utility [patent_app_number] => 13/180495 [patent_app_country] => US [patent_app_date] => 2011-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 12969 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13180495 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8540537 [patent_doc_number] => 08316266 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-20 [patent_title] => 'Shifting bits in different scan paths with steady TMS' [patent_app_type] => utility [patent_app_number] => 13/179126 [patent_app_country] => US [patent_app_date] => 2011-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 4099 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13179126 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7512792 [patent_doc_number] => 20110258502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-20 [patent_title] => 'WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE' [patent_app_type] => utility [patent_app_number] => 13/175484 [patent_app_country] => US [patent_app_date] => 2011-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4543 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20110258502.pdf [firstpage_image] =>[orig_patent_app_number] => 13175484 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9752318 [patent_doc_number] => 08843808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-23 [patent_title] => 'System and method to flag a source of data corruption in a storage subsystem using persistent source identifier bits' [patent_app_type] => utility [patent_app_number] => 13/173184 [patent_app_country] => US [patent_app_date] => 2011-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5464 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13173184 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8588726 [patent_doc_number] => 20130007547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'EFFICIENT WRAPPER CELL DESIGN FOR SCAN TESTING OF INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 13/173144 [patent_app_country] => US [patent_app_date] => 2011-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4585 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13173144 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9458641 [patent_doc_number] => 08719667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-06 [patent_title] => 'Method for adding redundancy data to a distributed data storage system and corresponding device' [patent_app_type] => utility [patent_app_number] => 13/135260 [patent_app_country] => US [patent_app_date] => 2011-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 7314 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13135260 [rel_patent_id] =>[rel_patent_doc_number] =>)