Search

Cynthia H. Britt

Examiner (ID: 6795, Phone: (571)272-3815 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2117, 2133, 2111, 2138
Total Applications
1845
Issued Applications
1687
Pending Applications
84
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9300195 [patent_doc_number] => 08648426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-11 [patent_title] => 'Tunneling transistors' [patent_app_type] => utility [patent_app_number] => 12/971393 [patent_app_country] => US [patent_app_date] => 2010-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2864 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12971393 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/971393
Tunneling transistors Dec 16, 2010 Issued
Array ( [id] => 5963168 [patent_doc_number] => 20110147793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'SiGe HETEROJUNCTION BIPOLAR TRANSISTOR MULTI-FINGER STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/971063 [patent_app_country] => US [patent_app_date] => 2010-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3000 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20110147793.pdf [firstpage_image] =>[orig_patent_app_number] => 12971063 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/971063
SiGe heterojunction bipolar transistor multi-finger structure Dec 16, 2010 Issued
Array ( [id] => 8248964 [patent_doc_number] => 20120153294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-21 [patent_title] => 'Semiconductor Structures Having Directly Bonded Diamond Heat Sinks and Methods for Making Such Structures' [patent_app_type] => utility [patent_app_number] => 12/971224 [patent_app_country] => US [patent_app_date] => 2010-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1755 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20120153294.pdf [firstpage_image] =>[orig_patent_app_number] => 12971224 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/971224
Semiconductor structures having directly bonded diamond heat sinks and methods for making such structures Dec 16, 2010 Issued
Array ( [id] => 8165969 [patent_doc_number] => 20120104361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'TRANSISTOR USING SOURCE ELECTRODE AND DRAIN ELECTRODE HAVING POINTED PORTIONS' [patent_app_type] => utility [patent_app_number] => 12/970962 [patent_app_country] => US [patent_app_date] => 2010-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1213 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20120104361.pdf [firstpage_image] =>[orig_patent_app_number] => 12970962 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/970962
TRANSISTOR USING SOURCE ELECTRODE AND DRAIN ELECTRODE HAVING POINTED PORTIONS Dec 16, 2010 Abandoned
Array ( [id] => 8578195 [patent_doc_number] => 08344406 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-01 [patent_title] => 'Light emitting diode package and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 12/970976 [patent_app_country] => US [patent_app_date] => 2010-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2539 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12970976 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/970976
Light emitting diode package and manufacturing method thereof Dec 16, 2010 Issued
Array ( [id] => 8629827 [patent_doc_number] => 08361899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-29 [patent_title] => 'Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturing' [patent_app_type] => utility [patent_app_number] => 12/970784 [patent_app_country] => US [patent_app_date] => 2010-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 3442 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12970784 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/970784
Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturing Dec 15, 2010 Issued
Array ( [id] => 8166035 [patent_doc_number] => 20120104388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'THREE-DIMENSIONAL STACKED SEMICONDUCTOR INTEGRATED CIRCUIT AND TSV REPAIR METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/970923 [patent_app_country] => US [patent_app_date] => 2010-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4373 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20120104388.pdf [firstpage_image] =>[orig_patent_app_number] => 12970923 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/970923
THREE-DIMENSIONAL STACKED SEMICONDUCTOR INTEGRATED CIRCUIT AND TSV REPAIR METHOD THEREOF Dec 15, 2010 Abandoned
Array ( [id] => 8435987 [patent_doc_number] => 08283758 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-09 [patent_title] => 'Microelectronic packages with enhanced heat dissipation and methods of manufacturing' [patent_app_type] => utility [patent_app_number] => 12/970729 [patent_app_country] => US [patent_app_date] => 2010-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3032 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12970729 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/970729
Microelectronic packages with enhanced heat dissipation and methods of manufacturing Dec 15, 2010 Issued
Array ( [id] => 6126838 [patent_doc_number] => 20110086489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'METHODS OF MANUFACTURING A HYBRID ELECTRICAL CONTACT' [patent_app_type] => utility [patent_app_number] => 12/970694 [patent_app_country] => US [patent_app_date] => 2010-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6791 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20110086489.pdf [firstpage_image] =>[orig_patent_app_number] => 12970694 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/970694
Methods of manufacturing a hybrid electrical contact Dec 15, 2010 Issued
Array ( [id] => 9031463 [patent_doc_number] => 20130234101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-12 [patent_title] => 'NON-VOLATILE MEMORY DEVICE AND PRODUCTION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/884331 [patent_app_country] => US [patent_app_date] => 2010-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 27095 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13884331 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/884331
Non-volatile memory device and production method thereof Nov 21, 2010 Issued
Array ( [id] => 8458565 [patent_doc_number] => 08294236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'Semiconductor device having dual-STI and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 12/946311 [patent_app_country] => US [patent_app_date] => 2010-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 32 [patent_no_of_words] => 9767 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12946311 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/946311
Semiconductor device having dual-STI and manufacturing method thereof Nov 14, 2010 Issued
Array ( [id] => 6145232 [patent_doc_number] => 20110017970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'SELF-ALIGN PLANERIZED BOTTOM ELECTRODE PHASE CHANGE MEMORY AND MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 12/899991 [patent_app_country] => US [patent_app_date] => 2010-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5004 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20110017970.pdf [firstpage_image] =>[orig_patent_app_number] => 12899991 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/899991
Self-align planerized bottom electrode phase change memory and manufacturing method Oct 6, 2010 Issued
Array ( [id] => 8487022 [patent_doc_number] => 20120286430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-15 [patent_title] => 'Method of Producing a Semiconductor Device and Semiconductor Device Having a Through-Wafer Interconnect' [patent_app_type] => utility [patent_app_number] => 13/499899 [patent_app_country] => US [patent_app_date] => 2010-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3597 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13499899 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/499899
Method of producing a semiconductor device and semiconductor device having a through-wafer interconnect Sep 27, 2010 Issued
Array ( [id] => 4634353 [patent_doc_number] => 08012803 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-06 [patent_title] => 'Vertically stacked pre-packaged integrated circuit chips' [patent_app_type] => utility [patent_app_number] => 12/891439 [patent_app_country] => US [patent_app_date] => 2010-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4112 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/012/08012803.pdf [firstpage_image] =>[orig_patent_app_number] => 12891439 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/891439
Vertically stacked pre-packaged integrated circuit chips Sep 26, 2010 Issued
Array ( [id] => 8474439 [patent_doc_number] => 20120273846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'Sensor for Detecting a Component of a Gas Mixture' [patent_app_type] => utility [patent_app_number] => 13/505672 [patent_app_country] => US [patent_app_date] => 2010-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2853 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13505672 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/505672
Sensor for detecting a component of a gas mixture Sep 19, 2010 Issued
Array ( [id] => 6256146 [patent_doc_number] => 20100295116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-25 [patent_title] => 'Semiconductor Device and Manufacturing Method Thereof' [patent_app_type] => utility [patent_app_number] => 12/850783 [patent_app_country] => US [patent_app_date] => 2010-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 9896 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0295/20100295116.pdf [firstpage_image] =>[orig_patent_app_number] => 12850783 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/850783
Semiconductor device and manufacturing method thereof Aug 4, 2010 Issued
Array ( [id] => 6397326 [patent_doc_number] => 20100304546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR THIN FILM, WHICH IS SUBJECTED TO HEAT TREATMENT TO HAVE ALIGNMENT MARK, CRYSTALLIZING METHOD FOR THE SEMICONDUCTOR THIN FILM, AND CRYSTALLIZING APPARATUS FOR THE SEMICONDUCTOR THIN FILM' [patent_app_type] => utility [patent_app_number] => 12/838206 [patent_app_country] => US [patent_app_date] => 2010-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 19720 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0304/20100304546.pdf [firstpage_image] =>[orig_patent_app_number] => 12838206 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/838206
Semiconductor device including semiconductor thin film, which is subjected to heat treatment to have alignment mark, crystallizing method for the semiconductor thin film, and crystallizing apparatus for the semiconductor thin film Jul 15, 2010 Issued
Array ( [id] => 6273724 [patent_doc_number] => 20100255614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-07 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SAME' [patent_app_type] => utility [patent_app_number] => 12/817796 [patent_app_country] => US [patent_app_date] => 2010-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 10337 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0255/20100255614.pdf [firstpage_image] =>[orig_patent_app_number] => 12817796 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/817796
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SAME Jun 16, 2010 Abandoned
Array ( [id] => 6273779 [patent_doc_number] => 20100255634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-07 [patent_title] => 'Manufacturing method of bottom substrate of package' [patent_app_type] => utility [patent_app_number] => 12/801574 [patent_app_country] => US [patent_app_date] => 2010-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4687 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0255/20100255634.pdf [firstpage_image] =>[orig_patent_app_number] => 12801574 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/801574
Manufacturing method of bottom substrate of package Jun 14, 2010 Abandoned
Array ( [id] => 8214877 [patent_doc_number] => 08193568 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-05 [patent_title] => 'Nanocrystal based universal memory cells, and memory cells' [patent_app_type] => utility [patent_app_number] => 12/815109 [patent_app_country] => US [patent_app_date] => 2010-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 11971 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/193/08193568.pdf [firstpage_image] =>[orig_patent_app_number] => 12815109 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/815109
Nanocrystal based universal memory cells, and memory cells Jun 13, 2010 Issued
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