
Cynthia H. Britt
Examiner (ID: 6795, Phone: (571)272-3815 , Office: P/2117 )
| Most Active Art Unit | 2117 |
| Art Unit(s) | 2117, 2133, 2111, 2138 |
| Total Applications | 1845 |
| Issued Applications | 1687 |
| Pending Applications | 84 |
| Abandoned Applications | 105 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5088830
[patent_doc_number] => 20070228469
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-04
[patent_title] => 'THIN-FILM TRANSISTOR FORMED ON INSULATING SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 11/758217
[patent_app_country] => US
[patent_app_date] => 2007-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 8058
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0228/20070228469.pdf
[firstpage_image] =>[orig_patent_app_number] => 11758217
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/758217 | THIN-FILM TRANSISTOR FORMED ON INSULATING SUBSTRATE | Jun 4, 2007 | Abandoned |
Array
(
[id] => 5223854
[patent_doc_number] => 20070253120
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-01
[patent_title] => 'MAGNETORESISTIVE EFFECT ELEMENT AND MAGNETIC MEMORY'
[patent_app_type] => utility
[patent_app_number] => 11/737379
[patent_app_country] => US
[patent_app_date] => 2007-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 7538
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[patent_no_of_ind_claims] => 1
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[pdf_file] => publications/A1/0253/20070253120.pdf
[firstpage_image] =>[orig_patent_app_number] => 11737379
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/737379 | MAGNETORESISTIVE EFFECT ELEMENT AND MAGNETIC MEMORY | Apr 18, 2007 | Abandoned |
Array
(
[id] => 4870770
[patent_doc_number] => 20080197504
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-21
[patent_title] => 'SINGLE-SIDED, FLAT, NO LEAD, INTEGRATED CIRCUIT PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 11/697260
[patent_app_country] => US
[patent_app_date] => 2007-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2302
[patent_no_of_claims] => 22
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0197/20080197504.pdf
[firstpage_image] =>[orig_patent_app_number] => 11697260
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/697260 | Single-sided, flat, no lead, integrated circuit package | Apr 4, 2007 | Issued |
Array
(
[id] => 75216
[patent_doc_number] => 07750408
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-07-06
[patent_title] => 'Integrated circuit structure incorporating an inductor, a conductive sheet and a protection circuit'
[patent_app_type] => utility
[patent_app_number] => 11/692948
[patent_app_country] => US
[patent_app_date] => 2007-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 13590
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/750/07750408.pdf
[firstpage_image] =>[orig_patent_app_number] => 11692948
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/692948 | Integrated circuit structure incorporating an inductor, a conductive sheet and a protection circuit | Mar 28, 2007 | Issued |
Array
(
[id] => 5477
[patent_doc_number] => 07812399
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-10-12
[patent_title] => 'Semiconductor device comprising multi-layer rectangular gate electrode surrounded on four sides by sidewall spacer and implantation regions'
[patent_app_type] => utility
[patent_app_number] => 11/693408
[patent_app_country] => US
[patent_app_date] => 2007-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
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[patent_no_of_words] => 16547
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/812/07812399.pdf
[firstpage_image] =>[orig_patent_app_number] => 11693408
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/693408 | Semiconductor device comprising multi-layer rectangular gate electrode surrounded on four sides by sidewall spacer and implantation regions | Mar 28, 2007 | Issued |
Array
(
[id] => 4715371
[patent_doc_number] => 20080237893
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-02
[patent_title] => 'Anti Pad To Reduce Parasitic Capacitance And Improve Return Loss In A Semiconductor Die And Package'
[patent_app_type] => utility
[patent_app_number] => 11/691788
[patent_app_country] => US
[patent_app_date] => 2007-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] => publications/A1/0237/20080237893.pdf
[firstpage_image] =>[orig_patent_app_number] => 11691788
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/691788 | Anti Pad To Reduce Parasitic Capacitance And Improve Return Loss In A Semiconductor Die And Package | Mar 26, 2007 | Abandoned |
Array
(
[id] => 4715211
[patent_doc_number] => 20080237733
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-02
[patent_title] => 'STRUCTURE AND METHOD TO ENHANCE CHANNEL STRESS BY USING OPTIMIZED STI STRESS AND NITRIDE CAPPING LAYER STRESS'
[patent_app_type] => utility
[patent_app_number] => 11/691699
[patent_app_country] => US
[patent_app_date] => 2007-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6984
[patent_no_of_claims] => 20
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0237/20080237733.pdf
[firstpage_image] =>[orig_patent_app_number] => 11691699
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/691699 | STRUCTURE AND METHOD TO ENHANCE CHANNEL STRESS BY USING OPTIMIZED STI STRESS AND NITRIDE CAPPING LAYER STRESS | Mar 26, 2007 | Abandoned |
Array
(
[id] => 4739713
[patent_doc_number] => 20080233366
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-25
[patent_title] => 'STRUCTURE AND METHOD FOR SiCOH INTERFACES WITH INCREASED MECHANICAL STRENGTH'
[patent_app_type] => utility
[patent_app_number] => 11/690248
[patent_app_country] => US
[patent_app_date] => 2007-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5836
[patent_no_of_claims] => 32
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[pdf_file] => publications/A1/0233/20080233366.pdf
[firstpage_image] =>[orig_patent_app_number] => 11690248
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/690248 | Structure and method for porous SiCOH dielectric layers and adhesion promoting or etch stop layers having increased interfacial and mechanical strength | Mar 22, 2007 | Issued |
Array
(
[id] => 4737196
[patent_doc_number] => 20080230848
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-25
[patent_title] => 'STRUCTURE HAVING DUAL SILICIDE REGION AND RELATED METHOD'
[patent_app_type] => utility
[patent_app_number] => 11/689708
[patent_app_country] => US
[patent_app_date] => 2007-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1845
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0230/20080230848.pdf
[firstpage_image] =>[orig_patent_app_number] => 11689708
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/689708 | STRUCTURE HAVING DUAL SILICIDE REGION AND RELATED METHOD | Mar 21, 2007 | Abandoned |
Array
(
[id] => 5473
[patent_doc_number] => 07812396
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-10-12
[patent_title] => 'Semiconductor device with channel layer comprising different types of impurities'
[patent_app_type] => utility
[patent_app_number] => 11/688449
[patent_app_country] => US
[patent_app_date] => 2007-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
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[patent_no_of_words] => 9883
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/812/07812396.pdf
[firstpage_image] =>[orig_patent_app_number] => 11688449
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/688449 | Semiconductor device with channel layer comprising different types of impurities | Mar 19, 2007 | Issued |
Array
(
[id] => 4915694
[patent_doc_number] => 20080096294
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-24
[patent_title] => 'INTEGRATED CIRCUIT STRUCTURE, DISPLAY MODULE, AND INSPECTION METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 11/685149
[patent_app_country] => US
[patent_app_date] => 2007-03-12
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[pdf_file] => publications/A1/0096/20080096294.pdf
[firstpage_image] =>[orig_patent_app_number] => 11685149
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/685149 | INTEGRATED CIRCUIT STRUCTURE, DISPLAY MODULE, AND INSPECTION METHOD THEREOF | Mar 11, 2007 | Abandoned |
Array
(
[id] => 4695482
[patent_doc_number] => 20080217666
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-11
[patent_title] => 'CMOS IMAGE SENSOR AND METHOD OF FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/683059
[patent_app_country] => US
[patent_app_date] => 2007-03-07
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[pdf_file] => publications/A1/0217/20080217666.pdf
[firstpage_image] =>[orig_patent_app_number] => 11683059
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/683059 | CMOS IMAGE SENSOR AND METHOD OF FABRICATING THE SAME | Mar 6, 2007 | Abandoned |
Array
(
[id] => 8435892
[patent_doc_number] => 08283663
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-10-09
[patent_title] => 'Multichip device'
[patent_app_type] => utility
[patent_app_number] => 11/680659
[patent_app_country] => US
[patent_app_date] => 2007-03-01
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11680659
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/680659 | Multichip device | Feb 28, 2007 | Issued |
Array
(
[id] => 4723944
[patent_doc_number] => 20080203485
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-28
[patent_title] => 'STRAINED METAL GATE STRUCTURE FOR CMOS DEVICES WITH IMPROVED CHANNEL MOBILITY AND METHODS OF FORMING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/680108
[patent_app_country] => US
[patent_app_date] => 2007-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => publications/A1/0203/20080203485.pdf
[firstpage_image] =>[orig_patent_app_number] => 11680108
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/680108 | STRAINED METAL GATE STRUCTURE FOR CMOS DEVICES WITH IMPROVED CHANNEL MOBILITY AND METHODS OF FORMING THE SAME | Feb 27, 2007 | Abandoned |
Array
(
[id] => 132846
[patent_doc_number] => 07701067
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-04-20
[patent_title] => 'Method for manufacturing semiconductor package capable of potting thermosetting resin while being heated'
[patent_app_type] => utility
[patent_app_number] => 11/708582
[patent_app_country] => US
[patent_app_date] => 2007-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/07/701/07701067.pdf
[firstpage_image] =>[orig_patent_app_number] => 11708582
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/708582 | Method for manufacturing semiconductor package capable of potting thermosetting resin while being heated | Feb 20, 2007 | Issued |
Array
(
[id] => 4795356
[patent_doc_number] => 20080006942
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-10
[patent_title] => 'Bottom substrate of package on package and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/708568
[patent_app_country] => US
[patent_app_date] => 2007-02-21
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/708568 | Bottom substrate of package on package and manufacturing method thereof | Feb 20, 2007 | Abandoned |
Array
(
[id] => 196645
[patent_doc_number] => 07638418
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-12-29
[patent_title] => 'Wiring substrate of a semiconductor component comprising rubber-elastic pads embedded in said wiring substrate and method for producing the same'
[patent_app_type] => utility
[patent_app_number] => 11/676869
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/676869 | Wiring substrate of a semiconductor component comprising rubber-elastic pads embedded in said wiring substrate and method for producing the same | Feb 19, 2007 | Issued |
Array
(
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[patent_issue_date] => 2008-01-03
[patent_title] => 'Semiconductor device and manufacturing method of same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/708039 | Semiconductor device comprising chip on chip structure | Feb 19, 2007 | Issued |
Array
(
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[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-08-16
[patent_title] => 'APPARATUS AND METHOD OF MANUFACTURE FOR AN IMAGER EQUIPPED WITH A CROSS-TALK BARRIER'
[patent_app_type] => utility
[patent_app_number] => 11/674608
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[firstpage_image] =>[orig_patent_app_number] => 11674608
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/674608 | Apparatus and method of manufacture for an imager equipped with a cross-talk barrier | Feb 12, 2007 | Issued |
Array
(
[id] => 8676065
[patent_doc_number] => 08384181
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-02-26
[patent_title] => 'Schottky diode structure with silicon mesa and junction barrier Schottky wells'
[patent_app_type] => utility
[patent_app_number] => 11/673117
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/673117 | Schottky diode structure with silicon mesa and junction barrier Schottky wells | Feb 8, 2007 | Issued |