
Cynthia H. Britt
Examiner (ID: 6795, Phone: (571)272-3815 , Office: P/2117 )
| Most Active Art Unit | 2117 |
| Art Unit(s) | 2117, 2133, 2111, 2138 |
| Total Applications | 1845 |
| Issued Applications | 1687 |
| Pending Applications | 84 |
| Abandoned Applications | 105 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5705357
[patent_doc_number] => 20060194405
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-31
[patent_title] => 'Semiconductor device and method of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/266262
[patent_app_country] => US
[patent_app_date] => 2005-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3715
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0194/20060194405.pdf
[firstpage_image] =>[orig_patent_app_number] => 11266262
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/266262 | Semiconductor device and method of fabricating the same | Nov 3, 2005 | Abandoned |
Array
(
[id] => 911375
[patent_doc_number] => 07329940
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-02-12
[patent_title] => 'Semiconductor structure and method of manufacture'
[patent_app_type] => utility
[patent_app_number] => 11/163882
[patent_app_country] => US
[patent_app_date] => 2005-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 2601
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[patent_words_short_claim] => 100
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/329/07329940.pdf
[firstpage_image] =>[orig_patent_app_number] => 11163882
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/163882 | Semiconductor structure and method of manufacture | Nov 1, 2005 | Issued |
Array
(
[id] => 5805187
[patent_doc_number] => 20060091540
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-04
[patent_title] => 'Semiconductor chip with post-passivation scheme formed over passivation layer'
[patent_app_type] => utility
[patent_app_number] => 11/262182
[patent_app_country] => US
[patent_app_date] => 2005-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 3187
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0091/20060091540.pdf
[firstpage_image] =>[orig_patent_app_number] => 11262182
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/262182 | Semiconductor chip with passivation layer comprising metal interconnect and contact pads | Oct 27, 2005 | Issued |
Array
(
[id] => 7599510
[patent_doc_number] => 07582938
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-09-01
[patent_title] => 'I/O and power ESD protection circuits by enhancing substrate-bias in deep-submicron CMOS process'
[patent_app_type] => utility
[patent_app_number] => 11/258253
[patent_app_country] => US
[patent_app_date] => 2005-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 4249
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 310
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/582/07582938.pdf
[firstpage_image] =>[orig_patent_app_number] => 11258253
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/258253 | I/O and power ESD protection circuits by enhancing substrate-bias in deep-submicron CMOS process | Oct 24, 2005 | Issued |
Array
(
[id] => 5848694
[patent_doc_number] => 20060231906
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-19
[patent_title] => 'Structure for measuring gate misalignment and measuring method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/254081
[patent_app_country] => US
[patent_app_date] => 2005-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 5172
[patent_no_of_claims] => 14
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0231/20060231906.pdf
[firstpage_image] =>[orig_patent_app_number] => 11254081
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/254081 | Structure for measuring gate misalignment and measuring method thereof | Oct 18, 2005 | Abandoned |
Array
(
[id] => 5732916
[patent_doc_number] => 20060258033
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-16
[patent_title] => 'Active matrix substrate and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/254002
[patent_app_country] => US
[patent_app_date] => 2005-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 2561
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[pdf_file] => publications/A1/0258/20060258033.pdf
[firstpage_image] =>[orig_patent_app_number] => 11254002
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/254002 | Active matrix substrate and method for fabricating the same | Oct 18, 2005 | Abandoned |
Array
(
[id] => 5191988
[patent_doc_number] => 20070080470
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-04-12
[patent_title] => 'Leaded package integrated circuit stacking'
[patent_app_type] => utility
[patent_app_number] => 11/248662
[patent_app_country] => US
[patent_app_date] => 2005-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 3868
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 7
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0080/20070080470.pdf
[firstpage_image] =>[orig_patent_app_number] => 11248662
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/248662 | Leaded package integrated circuit stacking | Oct 10, 2005 | Issued |
Array
(
[id] => 5718570
[patent_doc_number] => 20060071343
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-06
[patent_title] => 'Semiconductor device and method of manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/239421
[patent_app_country] => US
[patent_app_date] => 2005-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4113
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0071/20060071343.pdf
[firstpage_image] =>[orig_patent_app_number] => 11239421
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/239421 | Semiconductor device and method of manufacturing semiconductor device | Sep 29, 2005 | Abandoned |
Array
(
[id] => 920165
[patent_doc_number] => 07321172
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-01-22
[patent_title] => 'Selective plating of package terminals'
[patent_app_type] => utility
[patent_app_number] => 11/227532
[patent_app_country] => US
[patent_app_date] => 2005-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 4197
[patent_no_of_claims] => 3
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[patent_words_short_claim] => 104
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/321/07321172.pdf
[firstpage_image] =>[orig_patent_app_number] => 11227532
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/227532 | Selective plating of package terminals | Sep 13, 2005 | Issued |
Array
(
[id] => 5611744
[patent_doc_number] => 20060113670
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-01
[patent_title] => 'Multi-layer wiring, method of manufacturing the same and thin film transistor having the same'
[patent_app_type] => utility
[patent_app_number] => 11/221492
[patent_app_country] => US
[patent_app_date] => 2005-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 5477
[patent_no_of_claims] => 47
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[pdf_file] => publications/A1/0113/20060113670.pdf
[firstpage_image] =>[orig_patent_app_number] => 11221492
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/221492 | Multi-layer wiring, method of manufacturing the same and thin film transistor having the same | Sep 6, 2005 | Abandoned |
Array
(
[id] => 5180765
[patent_doc_number] => 20070052107
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-08
[patent_title] => 'MULTI-LAYERED STRUCTURE AND FABRICATING METHOD THEREOF AND DUAL DAMASCENE STRUCTURE, INTERCONNECT STRUCTURE AND CAPACITOR'
[patent_app_type] => utility
[patent_app_number] => 11/162272
[patent_app_country] => US
[patent_app_date] => 2005-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 3118
[patent_no_of_claims] => 28
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[pdf_file] => publications/A1/0052/20070052107.pdf
[firstpage_image] =>[orig_patent_app_number] => 11162272
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/162272 | MULTI-LAYERED STRUCTURE AND FABRICATING METHOD THEREOF AND DUAL DAMASCENE STRUCTURE, INTERCONNECT STRUCTURE AND CAPACITOR | Sep 4, 2005 | Abandoned |
Array
(
[id] => 5898373
[patent_doc_number] => 20060043606
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-02
[patent_title] => 'Semiconductor device having laminated structure'
[patent_app_type] => utility
[patent_app_number] => 11/215121
[patent_app_country] => US
[patent_app_date] => 2005-08-31
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[patent_drawing_sheets_cnt] => 7
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[firstpage_image] =>[orig_patent_app_number] => 11215121
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/215121 | Semiconductor device having laminated structure | Aug 30, 2005 | Issued |
Array
(
[id] => 5145795
[patent_doc_number] => 20070045849
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-01
[patent_title] => 'Semiconductor structure having selective silicide-induced stress and a method of producing same'
[patent_app_type] => utility
[patent_app_number] => 11/216512
[patent_app_country] => US
[patent_app_date] => 2005-08-31
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 11216512
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/216512 | Semiconductor structure having selective silicide-induced stress and a method of producing same | Aug 30, 2005 | Issued |
Array
(
[id] => 5903586
[patent_doc_number] => 20060046464
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-02
[patent_title] => 'Wiring substrate and semiconductor device using the same'
[patent_app_type] => utility
[patent_app_number] => 11/211712
[patent_app_country] => US
[patent_app_date] => 2005-08-26
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 11211712
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/211712 | Wiring substrate and semiconductor device using the same | Aug 25, 2005 | Abandoned |
Array
(
[id] => 4496129
[patent_doc_number] => 07956428
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-06-07
[patent_title] => 'Microelectromechanical devices and fabrication methods'
[patent_app_type] => utility
[patent_app_number] => 11/205702
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[firstpage_image] =>[orig_patent_app_number] => 11205702
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/205702 | Microelectromechanical devices and fabrication methods | Aug 15, 2005 | Issued |
Array
(
[id] => 5708121
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[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-09
[patent_title] => 'Power semiconductor device for preventing punchthrough and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/202176
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 11202176
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/202176 | Power semiconductor device for preventing punchthrough and manufacturing method thereof | Aug 11, 2005 | Abandoned |
Array
(
[id] => 5152040
[patent_doc_number] => 20070034922
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-15
[patent_title] => 'Integrated surround gate multifunctional memory device'
[patent_app_type] => utility
[patent_app_number] => 11/202282
[patent_app_country] => US
[patent_app_date] => 2005-08-11
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[firstpage_image] =>[orig_patent_app_number] => 11202282
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/202282 | Integrated surround gate multifunctional memory device | Aug 10, 2005 | Abandoned |
Array
(
[id] => 5765908
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[patent_title] => 'Photoresist process to enable sloped passivation bondpad openings for ease of metal step coverings'
[patent_app_type] => utility
[patent_app_number] => 11/202462
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/202462 | Photoresist process to enable sloped passivation bondpad openings for ease of metal step coverings | Aug 10, 2005 | Abandoned |
Array
(
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[patent_kind] => A1
[patent_issue_date] => 2006-02-16
[patent_title] => 'Semiconductor device having dual-STI and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/200262
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[pdf_file] => publications/A1/0035/20060035437.pdf
[firstpage_image] =>[orig_patent_app_number] => 11200262
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/200262 | Semiconductor device having dual-STI and manufacturing method thereof | Aug 9, 2005 | Abandoned |
Array
(
[id] => 5838188
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[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-08
[patent_title] => 'Annular gate and technique for fabricating an annular gate'
[patent_app_type] => utility
[patent_app_number] => 11/010951
[patent_app_country] => US
[patent_app_date] => 2005-08-04
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[firstpage_image] =>[orig_patent_app_number] => 11010951
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/010951 | Annular gate and technique for fabricating an annular gate | Aug 3, 2005 | Issued |