Cynthia H. Britt

Array ( [id] => 7002390 [patent_doc_number] => 20050167703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Reduction of the contact resistance in organic field-effect transistors with palladium contacts by using phosphines and metal-containing phosphines' [patent_app_type] => utility [patent_app_number] => 11/045511 [patent_app_country] => US [patent_app_date] => 2005-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5579 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20050167703.pdf [firstpage_image] =>[orig_patent_app_number] => 11045511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7183174 [patent_doc_number] => 20050161726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Capacitor of a semiconductor device, memory device including the same and method of munufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/042111 [patent_app_country] => US [patent_app_date] => 2005-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6012 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20050161726.pdf [firstpage_image] =>[orig_patent_app_number] => 11042111 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7214198 [patent_doc_number] => 20050253214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-17 [patent_title] => 'Solid-state imaging device' [patent_app_type] => utility [patent_app_number] => 11/039782 [patent_app_country] => US [patent_app_date] => 2005-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7054 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20050253214.pdf [firstpage_image] =>[orig_patent_app_number] => 11039782 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6981103 [patent_doc_number] => 20050151171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-14 [patent_title] => 'JFET structure for integrated circuit and fabrication method' [patent_app_type] => utility [patent_app_number] => 11/038562 [patent_app_country] => US [patent_app_date] => 2005-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9772 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20050151171.pdf [firstpage_image] =>[orig_patent_app_number] => 11038562 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 436245 [patent_doc_number] => 07262503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-28 [patent_title] => 'Semiconductor constructions' [patent_app_type] => utility [patent_app_number] => 11/026822 [patent_app_country] => US [patent_app_date] => 2004-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 4767 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/262/07262503.pdf [firstpage_image] =>[orig_patent_app_number] => 11026822 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5645978 [patent_doc_number] => 20060131710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Advanced cavity structure for wafer level chip scale package' [patent_app_type] => utility [patent_app_number] => 11/020041 [patent_app_country] => US [patent_app_date] => 2004-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2479 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20060131710.pdf [firstpage_image] =>[orig_patent_app_number] => 11020041 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7072639 [patent_doc_number] => 20050145905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Solid-state imaging device and production method of the same' [patent_app_type] => utility [patent_app_number] => 11/004381 [patent_app_country] => US [patent_app_date] => 2004-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5895 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20050145905.pdf [firstpage_image] =>[orig_patent_app_number] => 11004381 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5611749 [patent_doc_number] => 20060113675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-01 [patent_title] => 'Barrier material and process for Cu interconnect' [patent_app_type] => utility [patent_app_number] => 11/001471 [patent_app_country] => US [patent_app_date] => 2004-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4232 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20060113675.pdf [firstpage_image] =>[orig_patent_app_number] => 11001471 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4981381 [patent_doc_number] => 20070085938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'Display device, method for manufacturing the same, and television apparatus' [patent_app_type] => utility [patent_app_number] => 10/578001 [patent_app_country] => US [patent_app_date] => 2004-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 58 [patent_no_of_words] => 31000 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 28 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20070085938.pdf [firstpage_image] =>[orig_patent_app_number] => 10578001 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6994136 [patent_doc_number] => 20050133912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Electrical connection structure' [patent_app_type] => utility [patent_app_number] => 10/995141 [patent_app_country] => US [patent_app_date] => 2004-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3157 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20050133912.pdf [firstpage_image] =>[orig_patent_app_number] => 10995141 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7140166 [patent_doc_number] => 20050116317 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-02 [patent_title] => 'Inductor for a system-on-a-chip and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/982782 [patent_app_country] => US [patent_app_date] => 2004-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8990 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20050116317.pdf [firstpage_image] =>[orig_patent_app_number] => 10982782 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7141774 [patent_doc_number] => 20050117442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-02 [patent_title] => 'Integrated semiconductor memory' [patent_app_type] => utility [patent_app_number] => 10/980151 [patent_app_country] => US [patent_app_date] => 2004-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4468 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20050117442.pdf [firstpage_image] =>[orig_patent_app_number] => 10980151 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4536643 [patent_doc_number] => 07872339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-18 [patent_title] => 'Vertically stacked pre-packaged integrated circuit chips' [patent_app_type] => utility [patent_app_number] => 10/968572 [patent_app_country] => US [patent_app_date] => 2004-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4103 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/872/07872339.pdf [firstpage_image] =>[orig_patent_app_number] => 10968572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7206304 [patent_doc_number] => 20050258506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-24 [patent_title] => 'Arrangement and process for protecting fuses/anti-fuses' [patent_app_type] => utility [patent_app_number] => 10/957492 [patent_app_country] => US [patent_app_date] => 2004-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1221 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20050258506.pdf [firstpage_image] =>[orig_patent_app_number] => 10957492 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6978038 [patent_doc_number] => 20050287756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Semiconductor device with resistor element and its manufacture method' [patent_app_type] => utility [patent_app_number] => 10/950451 [patent_app_country] => US [patent_app_date] => 2004-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4148 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20050287756.pdf [firstpage_image] =>[orig_patent_app_number] => 10950451 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6969742 [patent_doc_number] => 20050035452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-17 [patent_title] => 'Die-up ball grid array package including a substrate having an opening and method for making the same' [patent_app_type] => utility [patent_app_number] => 10/938955 [patent_app_country] => US [patent_app_date] => 2004-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6707 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20050035452.pdf [firstpage_image] =>[orig_patent_app_number] => 10938955 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 457673 [patent_doc_number] => 07245016 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-17 [patent_title] => 'Circuit layout structure' [patent_app_type] => utility [patent_app_number] => 10/711281 [patent_app_country] => US [patent_app_date] => 2004-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2725 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/245/07245016.pdf [firstpage_image] =>[orig_patent_app_number] => 10711281 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5817882 [patent_doc_number] => 20060022195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'SCRIBE LINE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 10/710761 [patent_app_country] => US [patent_app_date] => 2004-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1874 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20060022195.pdf [firstpage_image] =>[orig_patent_app_number] => 10710761 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7273106 [patent_doc_number] => 20040232557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Semiconductor device having a metal insulator metal capacitor' [patent_app_type] => new [patent_app_number] => 10/876481 [patent_app_country] => US [patent_app_date] => 2004-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3878 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20040232557.pdf [firstpage_image] =>[orig_patent_app_number] => 10876481 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6978061 [patent_doc_number] => 20050287779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Integrated circuit structure and method of fabrication' [patent_app_type] => utility [patent_app_number] => 10/877441 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3213 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20050287779.pdf [firstpage_image] =>[orig_patent_app_number] => 10877441 [rel_patent_id] =>[rel_patent_doc_number] =>)