Search

Cynthia H. Britt

Examiner (ID: 11869)

Most Active Art Unit
2117
Art Unit(s)
2117, 2111, 2133, 2138
Total Applications
1844
Issued Applications
1687
Pending Applications
80
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18720064 [patent_doc_number] => 11797409 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-10-24 [patent_title] => Method and system for managing transactions burstiness and generating signature thereof in a test environment [patent_app_type] => utility [patent_app_number] => 17/901858 [patent_app_country] => US [patent_app_date] => 2022-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7534 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17901858 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/901858
Method and system for managing transactions burstiness and generating signature thereof in a test environment Sep 1, 2022 Issued
Array ( [id] => 18385502 [patent_doc_number] => 11656278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Apparatus for device access port selection [patent_app_type] => utility [patent_app_number] => 17/823153 [patent_app_country] => US [patent_app_date] => 2022-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 58 [patent_no_of_words] => 17613 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17823153 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/823153
Apparatus for device access port selection Aug 29, 2022 Issued
Array ( [id] => 18095965 [patent_doc_number] => 20220414306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => SYSTEM AND METHOD FOR FORMAL FAULT PROPAGATION ANALYSIS [patent_app_type] => utility [patent_app_number] => 17/899210 [patent_app_country] => US [patent_app_date] => 2022-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8911 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17899210 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/899210
System and method for formal fault propagation analysis Aug 29, 2022 Issued
Array ( [id] => 19008863 [patent_doc_number] => 20240072934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => CODED SPREADING AND INTERLEAVING FOR MULTI-LEVEL CODING SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/822631 [patent_app_country] => US [patent_app_date] => 2022-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23832 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17822631 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/822631
Coded spreading and interleaving for multi-level coding systems Aug 25, 2022 Issued
Array ( [id] => 18515296 [patent_doc_number] => 20230231578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => METHOD AND SYSTEM FOR ON-ASIC ERROR CONTROL DECODING [patent_app_type] => utility [patent_app_number] => 17/894777 [patent_app_country] => US [patent_app_date] => 2022-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3547 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17894777 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/894777
Method and system for on-ASIC error control decoding Aug 23, 2022 Issued
Array ( [id] => 19374929 [patent_doc_number] => 12066490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Wrapper cell design and built-in self-test architecture for 3DIC test and diagnosis [patent_app_type] => utility [patent_app_number] => 17/893236 [patent_app_country] => US [patent_app_date] => 2022-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 7182 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17893236 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/893236
Wrapper cell design and built-in self-test architecture for 3DIC test and diagnosis Aug 22, 2022 Issued
Array ( [id] => 18037605 [patent_doc_number] => 20220381821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => 3D STACKED DIE TEST ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/885472 [patent_app_country] => US [patent_app_date] => 2022-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7107 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17885472 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/885472
3D stacked die test architecture Aug 9, 2022 Issued
Array ( [id] => 18781991 [patent_doc_number] => 11823756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Method and device for testing memory array structure, and storage medium [patent_app_type] => utility [patent_app_number] => 17/884928 [patent_app_country] => US [patent_app_date] => 2022-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8859 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884928 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/884928
Method and device for testing memory array structure, and storage medium Aug 9, 2022 Issued
Array ( [id] => 18855106 [patent_doc_number] => 11852680 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-12-26 [patent_title] => Test device and test method thereof [patent_app_type] => utility [patent_app_number] => 17/883633 [patent_app_country] => US [patent_app_date] => 2022-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7290 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17883633 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/883633
Test device and test method thereof Aug 8, 2022 Issued
Array ( [id] => 18973956 [patent_doc_number] => 20240054048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => MULTI-LAYER CODE RATE ARCHITECTURE FOR SPECIAL EVENT PROTECTION WITH REDUCED PERFORMANCE PENALTY [patent_app_type] => utility [patent_app_number] => 17/884432 [patent_app_country] => US [patent_app_date] => 2022-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11735 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884432 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/884432
Multi-layer code rate architecture for special event protection with reduced performance penalty Aug 8, 2022 Issued
Array ( [id] => 18038269 [patent_doc_number] => 20220382485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => JTAG REGISTERS WITH CONCURRENT INPUTS [patent_app_type] => utility [patent_app_number] => 17/883175 [patent_app_country] => US [patent_app_date] => 2022-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11962 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17883175 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/883175
JTAG registers with concurrent inputs Aug 7, 2022 Issued
Array ( [id] => 18198424 [patent_doc_number] => 20230051943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => METHOD FOR PROTECTING A RECONFIGURABLE DIGITAL INTEGRATED CIRCUIT AGAINST REVERSIBLE ERRORS [patent_app_type] => utility [patent_app_number] => 17/881649 [patent_app_country] => US [patent_app_date] => 2022-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6296 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17881649 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/881649
Method for protecting a reconfigurable digital integrated circuit against reversible errors Aug 4, 2022 Issued
Array ( [id] => 19259461 [patent_doc_number] => 12019515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Electronic device with erasure coding acceleration for distributed file systems and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/881872 [patent_app_country] => US [patent_app_date] => 2022-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6726 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17881872 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/881872
Electronic device with erasure coding acceleration for distributed file systems and operating method thereof Aug 4, 2022 Issued
Array ( [id] => 18208016 [patent_doc_number] => 20230054273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => QUANTUM SYSTEM CONTROLLER CONFIGURED FOR QUANTUM ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 17/816807 [patent_app_country] => US [patent_app_date] => 2022-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20980 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17816807 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/816807
Quantum system controller configured for quantum error correction Aug 1, 2022 Issued
Array ( [id] => 17991976 [patent_doc_number] => 20220358013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => Systems and Methods for Correcting Data Errors in Memory [patent_app_type] => utility [patent_app_number] => 17/873262 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8451 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873262 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/873262
Systems and methods for correcting data errors in memory Jul 25, 2022 Issued
Array ( [id] => 17985759 [patent_doc_number] => 20220351796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => WORKLOAD ADAPTIVE SCANS FOR MEMORY SUB-SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/867538 [patent_app_country] => US [patent_app_date] => 2022-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9661 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17867538 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/867538
Workload adaptive scans for memory sub-systems Jul 17, 2022 Issued
Array ( [id] => 18904005 [patent_doc_number] => 20240019490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => CONFIGURATION OF CONFIGURABLE TEST LOGIC [patent_app_type] => utility [patent_app_number] => 17/812937 [patent_app_country] => US [patent_app_date] => 2022-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7963 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17812937 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/812937
Configuration of configurable test logic Jul 14, 2022 Issued
Array ( [id] => 19458606 [patent_doc_number] => 12099091 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Cost-saving scheme for scan testing of 3D stack die [patent_app_type] => utility [patent_app_number] => 17/866342 [patent_app_country] => US [patent_app_date] => 2022-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7288 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17866342 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/866342
Cost-saving scheme for scan testing of 3D stack die Jul 14, 2022 Issued
Array ( [id] => 17961404 [patent_doc_number] => 20220341985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => INTEGRATED CIRCUIT DIE TEST ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/858122 [patent_app_country] => US [patent_app_date] => 2022-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5048 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17858122 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/858122
Integrated circuit die test architecture Jul 5, 2022 Issued
Array ( [id] => 19136824 [patent_doc_number] => 11971780 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Data error correction circuit and data transmission circuit [patent_app_type] => utility [patent_app_number] => 17/810025 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5865 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 364 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17810025 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/810025
Data error correction circuit and data transmission circuit Jun 29, 2022 Issued
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