Search

Cynthia H. Britt

Examiner (ID: 11869)

Most Active Art Unit
2117
Art Unit(s)
2117, 2111, 2133, 2138
Total Applications
1844
Issued Applications
1687
Pending Applications
80
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17931178 [patent_doc_number] => 20220326303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => GENERATING MULTIPLE PSEUDO STATIC CONTROL SIGNALS USING ON-CHIP JTAG STATE MACHINE [patent_app_type] => utility [patent_app_number] => 17/809616 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7970 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17809616 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/809616
Generating multiple pseudo static control signals using on-chip JTAG state machine Jun 28, 2022 Issued
Array ( [id] => 18098430 [patent_doc_number] => 20220416771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => EMBEDDED PATTERN GENERATOR [patent_app_type] => utility [patent_app_number] => 17/849417 [patent_app_country] => US [patent_app_date] => 2022-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15446 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17849417 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/849417
Embedded pattern generator Jun 23, 2022 Issued
Array ( [id] => 19393698 [patent_doc_number] => 20240283568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => A METHOD TO FACILITATE ADAPTIVE BIT LOADING BY INSERTION OF DUMMY BITS PRIOR TO INTERLEAVING [patent_app_type] => utility [patent_app_number] => 18/569311 [patent_app_country] => US [patent_app_date] => 2022-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11547 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18569311 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/569311
A METHOD TO FACILITATE ADAPTIVE BIT LOADING BY INSERTION OF DUMMY BITS PRIOR TO INTERLEAVING Jun 15, 2022 Abandoned
Array ( [id] => 18781082 [patent_doc_number] => 11822822 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Memory component having internal read-modify-write operation [patent_app_type] => utility [patent_app_number] => 17/824665 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8561 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824665 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/824665
Memory component having internal read-modify-write operation May 24, 2022 Issued
Array ( [id] => 17839580 [patent_doc_number] => 20220276885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => CONTROLLER FOR A MEMORY COMPONENT [patent_app_type] => utility [patent_app_number] => 17/745546 [patent_app_country] => US [patent_app_date] => 2022-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17745546 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/745546
Controller for a memory component May 15, 2022 Issued
Array ( [id] => 19243801 [patent_doc_number] => 12014247 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Systems and methods for compressed sensing measurement of long-range correlated noise [patent_app_type] => utility [patent_app_number] => 17/743850 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 20400 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17743850 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/743850
Systems and methods for compressed sensing measurement of long-range correlated noise May 12, 2022 Issued
Array ( [id] => 18872432 [patent_doc_number] => 11860228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Integrated circuit chip testing interface with reduced signal wires [patent_app_type] => utility [patent_app_number] => 17/742363 [patent_app_country] => US [patent_app_date] => 2022-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7223 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17742363 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/742363
Integrated circuit chip testing interface with reduced signal wires May 10, 2022 Issued
Array ( [id] => 18872428 [patent_doc_number] => 11860224 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Interposer instrumentation method and apparatus [patent_app_type] => utility [patent_app_number] => 17/739025 [patent_app_country] => US [patent_app_date] => 2022-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 50 [patent_no_of_words] => 11432 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17739025 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/739025
Interposer instrumentation method and apparatus May 5, 2022 Issued
Array ( [id] => 18644175 [patent_doc_number] => 11768239 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-09-26 [patent_title] => Method and apparatus for timing-annotated scan-chain testing using parallel testbench [patent_app_type] => utility [patent_app_number] => 17/662345 [patent_app_country] => US [patent_app_date] => 2022-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4167 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17662345 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/662345
Method and apparatus for timing-annotated scan-chain testing using parallel testbench May 5, 2022 Issued
Array ( [id] => 17794273 [patent_doc_number] => 20220253365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => ON-DIE LOGIC ANALYZER [patent_app_type] => utility [patent_app_number] => 17/729841 [patent_app_country] => US [patent_app_date] => 2022-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17729841 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/729841
On-die logic analyzer Apr 25, 2022 Issued
Array ( [id] => 18702571 [patent_doc_number] => 11789078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Electronic device comprising a memory accessible via a JTAG interface, and corresponding method of accessing a memory [patent_app_type] => utility [patent_app_number] => 17/714515 [patent_app_country] => US [patent_app_date] => 2022-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4566 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17714515 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/714515
Electronic device comprising a memory accessible via a JTAG interface, and corresponding method of accessing a memory Apr 5, 2022 Issued
Array ( [id] => 17722221 [patent_doc_number] => 20220214943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => METHOD OF CORRECTING ERRORS IN A MEMORY ARRAY AND METHOD OF SCREENING WEAK BITS IN THE SAME [patent_app_type] => utility [patent_app_number] => 17/703857 [patent_app_country] => US [patent_app_date] => 2022-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17210 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17703857 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/703857
Method of correcting errors in a memory array and method of screening weak bits in the same Mar 23, 2022 Issued
Array ( [id] => 18521200 [patent_doc_number] => 11711099 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-07-25 [patent_title] => Low gate-count encoding algorithm and hardware of flexible rate GLDPC ECC [patent_app_type] => utility [patent_app_number] => 17/702048 [patent_app_country] => US [patent_app_date] => 2022-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 30 [patent_no_of_words] => 8855 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17702048 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/702048
Low gate-count encoding algorithm and hardware of flexible rate GLDPC ECC Mar 22, 2022 Issued
Array ( [id] => 18650838 [patent_doc_number] => 20230296673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => DDR5 SDRAM DIMM SLOT DETECTION SYSTEM AND METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/701429 [patent_app_country] => US [patent_app_date] => 2022-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4415 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 397 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17701429 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/701429
DDR5 SDRAM DIMM slot detection system and method thereof Mar 21, 2022 Issued
Array ( [id] => 18527141 [patent_doc_number] => 11714131 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-08-01 [patent_title] => Circuit and method for scan testing [patent_app_type] => utility [patent_app_number] => 17/699900 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 11474 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17699900 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/699900
Circuit and method for scan testing Mar 20, 2022 Issued
Array ( [id] => 17693932 [patent_doc_number] => 20220201225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => SOFT FEC WITH PARITY CHECK [patent_app_type] => utility [patent_app_number] => 17/693931 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6899 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17693931 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/693931
Soft FEC with parity check Mar 13, 2022 Issued
Array ( [id] => 17689443 [patent_doc_number] => 20220196736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => AT-SPEED TEST ACCESS PORT OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/692057 [patent_app_country] => US [patent_app_date] => 2022-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13112 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17692057 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/692057
At-speed test access port operations Mar 9, 2022 Issued
Array ( [id] => 18629594 [patent_doc_number] => 20230288479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => APPARATUS AND METHOD FOR REUSING MANUFACTURING CONTENT ACROSS MULTI-CHIP PACKAGES [patent_app_type] => utility [patent_app_number] => 17/691160 [patent_app_country] => US [patent_app_date] => 2022-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7046 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17691160 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/691160
Apparatus and method for reusing manufacturing content across multi-chip packages Mar 9, 2022 Issued
Array ( [id] => 18548880 [patent_doc_number] => 11722243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Signalling coding and modulation method and demodulation and decoding method and device [patent_app_type] => utility [patent_app_number] => 17/652927 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 9007 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17652927 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/652927
Signalling coding and modulation method and demodulation and decoding method and device Feb 27, 2022 Issued
Array ( [id] => 19576126 [patent_doc_number] => 20240380418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => TRANSMISSION DEVICE, TRANSMISSION METHOD, RECEPTION DEVICE, AND RECEPTION METHOD [patent_app_type] => utility [patent_app_number] => 18/576756 [patent_app_country] => US [patent_app_date] => 2022-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 62963 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 1198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18576756 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/576756
TRANSMISSION DEVICE, TRANSMISSION METHOD, RECEPTION DEVICE, AND RECEPTION METHOD Feb 23, 2022 Abandoned
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