Search

Cynthia M Chin

Examiner (ID: 17337, Phone: (571)272-6021 , Office: P/2917 )

Most Active Art Unit
2917
Art Unit(s)
2917, 2915, 2911
Total Applications
4791
Issued Applications
4713
Pending Applications
18
Abandoned Applications
56

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9493334 [patent_doc_number] => 20140143740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-22 [patent_title] => 'POLYGON RECOVERY FOR VLSI MASK CORRECTION' [patent_app_type] => utility [patent_app_number] => 14/022690 [patent_app_country] => US [patent_app_date] => 2013-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4969 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14022690 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/022690
POLYGON RECOVERY FOR VLSI MASK CORRECTION Sep 9, 2013 Abandoned
13/835875 APPARATUS AND METHOD FOR REDUCING PEAK POWER USING ASYNCHRONOUS CIRCUIT DESIGN TECHNOLOGY Mar 14, 2013 Abandoned
Array ( [id] => 9367890 [patent_doc_number] => 20140077763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-20 [patent_title] => 'MULTI-ORIENTATION STAND FOR A PORTABLE ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 13/617817 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5115 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13617817 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/617817
MULTI-ORIENTATION STAND FOR A PORTABLE ELECTRONIC DEVICE Sep 13, 2012 Abandoned
Array ( [id] => 8753894 [patent_doc_number] => 20130088198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-11 [patent_title] => 'ELECTRIC CHARGING SYSTEM AND ELECTRIC CHARGING METHOD' [patent_app_type] => utility [patent_app_number] => 13/615564 [patent_app_country] => US [patent_app_date] => 2012-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9539 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13615564 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/615564
ELECTRIC CHARGING SYSTEM AND ELECTRIC CHARGING METHOD Sep 12, 2012 Abandoned
Array ( [id] => 9297213 [patent_doc_number] => 20140040847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'SYSTEM AND METHOD FOR GENERATING PHYSICAL DETERMINISTIC BOUNDARY INTERCONNECT FEATURES FOR DUAL PATTERNING TECHNOLOGIES' [patent_app_type] => utility [patent_app_number] => 13/564159 [patent_app_country] => US [patent_app_date] => 2012-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5290 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13564159 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/564159
SYSTEM AND METHOD FOR GENERATING PHYSICAL DETERMINISTIC BOUNDARY INTERCONNECT FEATURES FOR DUAL PATTERNING TECHNOLOGIES Jul 31, 2012 Abandoned
Array ( [id] => 8863729 [patent_doc_number] => 20130147431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'RECHARGE SYSTEMS AND METHODS' [patent_app_type] => utility [patent_app_number] => 13/558812 [patent_app_country] => US [patent_app_date] => 2012-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10864 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13558812 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/558812
RECHARGE SYSTEMS AND METHODS Jul 25, 2012 Abandoned
Array ( [id] => 8564098 [patent_doc_number] => 20120326669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'POWER TOOL STORAGE CASE' [patent_app_type] => utility [patent_app_number] => 13/478425 [patent_app_country] => US [patent_app_date] => 2012-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4397 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13478425 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/478425
POWER TOOL STORAGE CASE May 22, 2012 Abandoned
Array ( [id] => 8583369 [patent_doc_number] => 20130002190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'CHARGER, CHARGING SYSTEM, AND CHARGING METHOD' [patent_app_type] => utility [patent_app_number] => 13/634667 [patent_app_country] => US [patent_app_date] => 2012-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 13957 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13634667 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/634667
CHARGER, CHARGING SYSTEM, AND CHARGING METHOD Feb 12, 2012 Abandoned
13/287077 Formal Verification of Deadlock Property Oct 31, 2011 Abandoned
13/115820 Guided Exploration of Circuit Design States May 24, 2011 Abandoned
Array ( [id] => 8325984 [patent_doc_number] => 20120198394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'Method For Improving Circuit Design Robustness' [patent_app_type] => utility [patent_app_number] => 13/018204 [patent_app_country] => US [patent_app_date] => 2011-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7569 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13018204 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/018204
Method For Improving Circuit Design Robustness Jan 30, 2011 Abandoned
Array ( [id] => 5990289 [patent_doc_number] => 20110012641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-20 [patent_title] => 'CELL ARRANGEMENT METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/890233 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3591 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20110012641.pdf [firstpage_image] =>[orig_patent_app_number] => 12890233 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/890233
CELL ARRANGEMENT METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT Sep 23, 2010 Abandoned
Array ( [id] => 8959161 [patent_doc_number] => 08504955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-06 [patent_title] => 'Timing adjustment device and method thereof' [patent_app_type] => utility [patent_app_number] => 12/783310 [patent_app_country] => US [patent_app_date] => 2010-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 12103 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12783310 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/783310
Timing adjustment device and method thereof May 18, 2010 Issued
Array ( [id] => 6652410 [patent_doc_number] => 20100229134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'LAYOUT VERIFICATION METHOD' [patent_app_type] => utility [patent_app_number] => 12/700117 [patent_app_country] => US [patent_app_date] => 2010-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6664 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20100229134.pdf [firstpage_image] =>[orig_patent_app_number] => 12700117 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/700117
LAYOUT VERIFICATION METHOD Feb 3, 2010 Abandoned
Array ( [id] => 6368213 [patent_doc_number] => 20100088451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-08 [patent_title] => 'ARCHITECTURE VERIFYING APPARATUS, ARCHITECTURE VERIFYING METHOD, AND MEDIUM STORING ARCHITECTURE VERIFYING PROGRAM' [patent_app_type] => utility [patent_app_number] => 12/553034 [patent_app_country] => US [patent_app_date] => 2009-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8982 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20100088451.pdf [firstpage_image] =>[orig_patent_app_number] => 12553034 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/553034
ARCHITECTURE VERIFYING APPARATUS, ARCHITECTURE VERIFYING METHOD, AND MEDIUM STORING ARCHITECTURE VERIFYING PROGRAM Sep 1, 2009 Abandoned
Array ( [id] => 6281519 [patent_doc_number] => 20100257503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-07 [patent_title] => 'POST-ROUTING COUPLING FIXES FOR INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/417136 [patent_app_country] => US [patent_app_date] => 2009-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3370 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0257/20100257503.pdf [firstpage_image] =>[orig_patent_app_number] => 12417136 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/417136
POST-ROUTING COUPLING FIXES FOR INTEGRATED CIRCUITS Apr 1, 2009 Abandoned
Array ( [id] => 5477918 [patent_doc_number] => 20090200875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-13 [patent_title] => 'Apparatus for supporting design of semiconductor integrated circuit device and method for designing semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 12/320881 [patent_app_country] => US [patent_app_date] => 2009-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9354 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20090200875.pdf [firstpage_image] =>[orig_patent_app_number] => 12320881 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/320881
Apparatus for supporting design of semiconductor integrated circuit device and method for designing semiconductor integrated circuit device Feb 5, 2009 Abandoned
Array ( [id] => 7679454 [patent_doc_number] => 20100107133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-29 [patent_title] => 'Method for increasing cell uniformity in an integrated circuit by adjusting cell inputs to design process' [patent_app_type] => utility [patent_app_number] => 12/288793 [patent_app_country] => US [patent_app_date] => 2008-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4016 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20100107133.pdf [firstpage_image] =>[orig_patent_app_number] => 12288793 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/288793
Method for increasing cell uniformity in an integrated circuit by adjusting cell inputs to design process Oct 22, 2008 Abandoned
Array ( [id] => 4722925 [patent_doc_number] => 20080244499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'APPARATUS AND DESIGN METHOD FOR CIRCUIT OF SEMICONDUCTOR DEVICE ETC' [patent_app_type] => utility [patent_app_number] => 12/135579 [patent_app_country] => US [patent_app_date] => 2008-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5085 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244499.pdf [firstpage_image] =>[orig_patent_app_number] => 12135579 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/135579
APPARATUS AND DESIGN METHOD FOR CIRCUIT OF SEMICONDUCTOR DEVICE ETC Jun 8, 2008 Abandoned
Array ( [id] => 5574169 [patent_doc_number] => 20090141530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'STRUCTURE FOR IMPLEMENTING ENHANCED CONTENT ADDRESSABLE MEMORY PERFORMANCE CAPABILITY' [patent_app_type] => utility [patent_app_number] => 12/110582 [patent_app_country] => US [patent_app_date] => 2008-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5277 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20090141530.pdf [firstpage_image] =>[orig_patent_app_number] => 12110582 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/110582
STRUCTURE FOR IMPLEMENTING ENHANCED CONTENT ADDRESSABLE MEMORY PERFORMANCE CAPABILITY Apr 27, 2008 Abandoned
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