Search

D. Gabrielle Brouillette

Examiner (ID: 5484)

Most Active Art Unit
1502
Art Unit(s)
1615, 1502, 1721
Total Applications
827
Issued Applications
554
Pending Applications
72
Abandoned Applications
201

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8891700 [patent_doc_number] => 20130164884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'ASSEMBLY OF QUASICRYSTALLINE PHOTONIC HETEROSTRUCTURES' [patent_app_type] => utility [patent_app_number] => 13/773248 [patent_app_country] => US [patent_app_date] => 2013-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2839 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13773248 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/773248
ASSEMBLY OF QUASICRYSTALLINE PHOTONIC HETEROSTRUCTURES Feb 20, 2013 Abandoned
Array ( [id] => 8880834 [patent_doc_number] => 20130154018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'SEMICONDUCTOR DEVICE COMPRISING SELF-ALIGNED CONTACT BARS AND METAL LINES WITH INCREASED VIA LANDING REGIONS' [patent_app_type] => utility [patent_app_number] => 13/769446 [patent_app_country] => US [patent_app_date] => 2013-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7937 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13769446 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/769446
Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regions Feb 17, 2013 Issued
Array ( [id] => 10152031 [patent_doc_number] => 09184331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-10 [patent_title] => 'Method for reducing tilt of optical unit during manufacture of image sensor' [patent_app_type] => utility [patent_app_number] => 13/766568 [patent_app_country] => US [patent_app_date] => 2013-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 3604 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13766568 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/766568
Method for reducing tilt of optical unit during manufacture of image sensor Feb 12, 2013 Issued
Array ( [id] => 8829366 [patent_doc_number] => 20130130411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'Interleaf for Leadframe Identification' [patent_app_type] => utility [patent_app_number] => 13/746067 [patent_app_country] => US [patent_app_date] => 2013-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2897 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13746067 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/746067
Interleaf for Leadframe Identification Jan 20, 2013 Abandoned
Array ( [id] => 13093647 [patent_doc_number] => 10066158 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-04 [patent_title] => Molded nanoparticle phosphor for light emitting applications [patent_app_type] => utility [patent_app_number] => 13/743414 [patent_app_country] => US [patent_app_date] => 2013-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3114 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13743414 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/743414
Molded nanoparticle phosphor for light emitting applications Jan 16, 2013 Issued
Array ( [id] => 10870142 [patent_doc_number] => 08895337 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-11-25 [patent_title] => 'Method of fabricating vertically aligned group III-V nanowires' [patent_app_type] => utility [patent_app_number] => 13/743433 [patent_app_country] => US [patent_app_date] => 2013-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5769 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13743433 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/743433
Method of fabricating vertically aligned group III-V nanowires Jan 16, 2013 Issued
Array ( [id] => 10525767 [patent_doc_number] => 09252289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-02 [patent_title] => 'Non-volatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/743485 [patent_app_country] => US [patent_app_date] => 2013-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2802 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13743485 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/743485
Non-volatile semiconductor memory device Jan 16, 2013 Issued
Array ( [id] => 10035334 [patent_doc_number] => 09076655 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-07 [patent_title] => 'Semiconductor device and method of forming through-silicon-via with sacrificial layer' [patent_app_type] => utility [patent_app_number] => 13/743054 [patent_app_country] => US [patent_app_date] => 2013-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 26 [patent_no_of_words] => 7706 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13743054 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/743054
Semiconductor device and method of forming through-silicon-via with sacrificial layer Jan 15, 2013 Issued
Array ( [id] => 8950726 [patent_doc_number] => 20130196507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-01 [patent_title] => 'Method Of Depositing Metals Using High Frequency Plasma' [patent_app_type] => utility [patent_app_number] => 13/742596 [patent_app_country] => US [patent_app_date] => 2013-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6107 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13742596 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/742596
Method of depositing metals using high frequency plasma Jan 15, 2013 Issued
Array ( [id] => 10118605 [patent_doc_number] => 09153493 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-10-06 [patent_title] => 'System for separating devices from a semiconductor wafer' [patent_app_type] => utility [patent_app_number] => 13/742562 [patent_app_country] => US [patent_app_date] => 2013-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 3240 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13742562 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/742562
System for separating devices from a semiconductor wafer Jan 15, 2013 Issued
Array ( [id] => 9491172 [patent_doc_number] => 20140141578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-22 [patent_title] => 'LOCAL TAILORING OF FINGERS IN MULTI-FINGER FIN FIELD EFFECT TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 13/741978 [patent_app_country] => US [patent_app_date] => 2013-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8230 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13741978 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/741978
LOCAL TAILORING OF FINGERS IN MULTI-FINGER FIN FIELD EFFECT TRANSISTORS Jan 14, 2013 Abandoned
Array ( [id] => 10059936 [patent_doc_number] => 09099299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-04 [patent_title] => 'Hard mask removal method' [patent_app_type] => utility [patent_app_number] => 13/737664 [patent_app_country] => US [patent_app_date] => 2013-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6344 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13737664 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/737664
Hard mask removal method Jan 8, 2013 Issued
Array ( [id] => 9792794 [patent_doc_number] => 20150004738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/371550 [patent_app_country] => US [patent_app_date] => 2013-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9279 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14371550 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/371550
Method of manufacturing an image sensor by joining a pixel circuit substrate and a logic circuit substrate and thereafter thinning the pixel circuit substrate Jan 7, 2013 Issued
Array ( [id] => 9869193 [patent_doc_number] => 08956965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-17 [patent_title] => 'Display panel manufacturing method, display panel, and display apparatus' [patent_app_type] => utility [patent_app_number] => 13/733958 [patent_app_country] => US [patent_app_date] => 2013-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 31 [patent_no_of_words] => 8961 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13733958 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/733958
Display panel manufacturing method, display panel, and display apparatus Jan 3, 2013 Issued
Array ( [id] => 9792796 [patent_doc_number] => 20150004740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'SILICON SOLAR CELL MODULE USING CONDUCTIVE NPASTE AS ELECTRODE AND METHOD FOR MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 14/371377 [patent_app_country] => US [patent_app_date] => 2012-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6415 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14371377 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/371377
Silicon solar cell module using conductive npaste as electrode and method for manufacturing same Dec 27, 2012 Issued
Array ( [id] => 11304613 [patent_doc_number] => 09511999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-06 [patent_title] => 'Thin film capping' [patent_app_type] => utility [patent_app_number] => 14/365235 [patent_app_country] => US [patent_app_date] => 2012-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 21 [patent_no_of_words] => 6379 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14365235 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/365235
Thin film capping Dec 16, 2012 Issued
Array ( [id] => 9518361 [patent_doc_number] => 20140154853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'METHOD FOR MANUFACTURING N-TYPE MOSFET' [patent_app_type] => utility [patent_app_number] => 13/878046 [patent_app_country] => US [patent_app_date] => 2012-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2334 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13878046 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/878046
Method for manufacturing N-type MOSFET Dec 6, 2012 Issued
Array ( [id] => 9482914 [patent_doc_number] => 08728864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-20 [patent_title] => 'Method of fabricating a memory card using SIP/SMT hybrid technology' [patent_app_type] => utility [patent_app_number] => 13/685288 [patent_app_country] => US [patent_app_date] => 2012-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 4322 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13685288 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/685288
Method of fabricating a memory card using SIP/SMT hybrid technology Nov 25, 2012 Issued
Array ( [id] => 8733197 [patent_doc_number] => 20130078766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/676696 [patent_app_country] => US [patent_app_date] => 2012-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13702 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13676696 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/676696
METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS Nov 13, 2012 Abandoned
Array ( [id] => 9474369 [patent_doc_number] => 20140131832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR LAYOUT PATTERN, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/674965 [patent_app_country] => US [patent_app_date] => 2012-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4593 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13674965 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/674965
Method for manufacturing semiconductor layout pattern, method for manufacturing semiconductor device, and semiconductor device Nov 12, 2012 Issued
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