Search

D. Gabrielle Brouillette

Examiner (ID: 5484)

Most Active Art Unit
1502
Art Unit(s)
1615, 1502, 1721
Total Applications
827
Issued Applications
554
Pending Applications
72
Abandoned Applications
201

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11079186 [patent_doc_number] => 20160276150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'PULSED PLASMA FOR FILM DEPOSITION' [patent_app_type] => utility [patent_app_number] => 15/073444 [patent_app_country] => US [patent_app_date] => 2016-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7676 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15073444 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/073444
Pulsed plasma for film deposition Mar 16, 2016 Issued
Array ( [id] => 11615473 [patent_doc_number] => 09653336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-16 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 15/073219 [patent_app_country] => US [patent_app_date] => 2016-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 16636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15073219 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/073219
Semiconductor device and manufacturing method thereof Mar 16, 2016 Issued
Array ( [id] => 11087580 [patent_doc_number] => 20160284548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'METHOD OF DOPING SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 15/073455 [patent_app_country] => US [patent_app_date] => 2016-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2665 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15073455 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/073455
Method of doping substrate Mar 16, 2016 Issued
Array ( [id] => 12478062 [patent_doc_number] => 09991275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 15/057412 [patent_app_country] => US [patent_app_date] => 2016-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 11111 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15057412 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/057412
Semiconductor memory device Feb 29, 2016 Issued
Array ( [id] => 10809644 [patent_doc_number] => 20160155804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-02 [patent_title] => 'Method of Fabricating Fin-Field Effect Transistors (FINFETS) Having Different Fin Widths' [patent_app_type] => utility [patent_app_number] => 15/013647 [patent_app_country] => US [patent_app_date] => 2016-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 8347 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15013647 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/013647
Method of fabricating fin-field effect transistors (finFETs) having different fin widths Feb 1, 2016 Issued
Array ( [id] => 12314820 [patent_doc_number] => 09941326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-10 [patent_title] => Method of manufacturing an image sensor by joining a pixel circuit substrate and a logic circuit substrate and thereafter thinning the pixel circuit substrate [patent_app_type] => utility [patent_app_number] => 14/989508 [patent_app_country] => US [patent_app_date] => 2016-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 9036 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14989508 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/989508
Method of manufacturing an image sensor by joining a pixel circuit substrate and a logic circuit substrate and thereafter thinning the pixel circuit substrate Jan 5, 2016 Issued
Array ( [id] => 11187559 [patent_doc_number] => 09418970 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-16 [patent_title] => 'Redistribution layers for microfeature workpieces, and associated systems and methods' [patent_app_type] => utility [patent_app_number] => 14/984354 [patent_app_country] => US [patent_app_date] => 2015-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 5578 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14984354 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/984354
Redistribution layers for microfeature workpieces, and associated systems and methods Dec 29, 2015 Issued
Array ( [id] => 11564779 [patent_doc_number] => 09627374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-18 [patent_title] => 'Electronic circuits including a MOSFET and a dual-gate JFET' [patent_app_type] => utility [patent_app_number] => 14/979337 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11161 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14979337 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/979337
Electronic circuits including a MOSFET and a dual-gate JFET Dec 21, 2015 Issued
Array ( [id] => 11346282 [patent_doc_number] => 09530698 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-12-27 [patent_title] => 'Method and structure for forming FinFET CMOS with dual doped STI regions' [patent_app_type] => utility [patent_app_number] => 14/968230 [patent_app_country] => US [patent_app_date] => 2015-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6050 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14968230 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/968230
Method and structure for forming FinFET CMOS with dual doped STI regions Dec 13, 2015 Issued
Array ( [id] => 10761732 [patent_doc_number] => 20160107885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'Method for the fabrication of thin-film transistors together with other components on a substrate' [patent_app_type] => utility [patent_app_number] => 14/862504 [patent_app_country] => US [patent_app_date] => 2015-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2764 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14862504 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/862504
Method for the fabrication of thin-film transistors together with other components on a substrate Sep 22, 2015 Issued
Array ( [id] => 10725611 [patent_doc_number] => 20160071760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-10 [patent_title] => 'HIGH RESISTIVITY SILICON-ON-INSULATOR WAFER MANUFACTURING METHOD FOR REDUCING SUBSTRATE LOSS' [patent_app_type] => utility [patent_app_number] => 14/835093 [patent_app_country] => US [patent_app_date] => 2015-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6204 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14835093 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/835093
High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss Aug 24, 2015 Issued
Array ( [id] => 11725291 [patent_doc_number] => 09698157 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-04 [patent_title] => 'Microstructure device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/834552 [patent_app_country] => US [patent_app_date] => 2015-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 5946 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14834552 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/834552
Microstructure device and method for manufacturing the same Aug 24, 2015 Issued
Array ( [id] => 11014472 [patent_doc_number] => 20160211426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'LIGHT EMITTING DIODE MODULE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/834690 [patent_app_country] => US [patent_app_date] => 2015-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1856 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14834690 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/834690
Light emitting diode module and method of manufacturing the same Aug 24, 2015 Issued
Array ( [id] => 11475736 [patent_doc_number] => 20170062519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'IMPLEMENTING MAGNETIC MEMORY INTEGRATION WITH CMOS DRIVING CIRCUITS' [patent_app_type] => utility [patent_app_number] => 14/835021 [patent_app_country] => US [patent_app_date] => 2015-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 6447 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14835021 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/835021
Implementing magnetic memory integration with CMOS driving circuits Aug 24, 2015 Issued
Array ( [id] => 11051075 [patent_doc_number] => 20160248035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/835087 [patent_app_country] => US [patent_app_date] => 2015-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11959 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14835087 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/835087
LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME Aug 24, 2015 Abandoned
Array ( [id] => 11417604 [patent_doc_number] => 09564437 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-02-07 [patent_title] => 'Method and structure for forming FinFET CMOS with dual doped STI regions' [patent_app_type] => utility [patent_app_number] => 14/834789 [patent_app_country] => US [patent_app_date] => 2015-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6017 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14834789 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/834789
Method and structure for forming FinFET CMOS with dual doped STI regions Aug 24, 2015 Issued
Array ( [id] => 11087758 [patent_doc_number] => 20160284727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/834636 [patent_app_country] => US [patent_app_date] => 2015-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8140 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14834636 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/834636
Semiconductor memory device Aug 24, 2015 Issued
Array ( [id] => 12195762 [patent_doc_number] => 09899499 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss' [patent_app_type] => utility [patent_app_number] => 14/835086 [patent_app_country] => US [patent_app_date] => 2015-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6395 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14835086 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/835086
High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss Aug 24, 2015 Issued
Array ( [id] => 11259432 [patent_doc_number] => 09484337 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-01 [patent_title] => 'Circuit protection device' [patent_app_type] => utility [patent_app_number] => 14/835150 [patent_app_country] => US [patent_app_date] => 2015-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2005 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14835150 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/835150
Circuit protection device Aug 24, 2015 Issued
Array ( [id] => 10389504 [patent_doc_number] => 20150274511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'Semiconductor Package And Manufacturing Method Thereof' [patent_app_type] => utility [patent_app_number] => 14/739345 [patent_app_country] => US [patent_app_date] => 2015-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3706 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14739345 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/739345
Semiconductor Package And Manufacturing Method Thereof Jun 14, 2015 Abandoned
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