Search

D Margaret M Seaman

Examiner (ID: 9100, Phone: (571)272-0694 , Office: P/1625 )

Most Active Art Unit
1625
Art Unit(s)
1612, 1621, 1625, 1203
Total Applications
3010
Issued Applications
2200
Pending Applications
275
Abandoned Applications
535

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 198902 [patent_doc_number] => 07639548 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-12-29 [patent_title] => 'Semiconductor device having variable parameter selection based on temperature and test method' [patent_app_type] => utility [patent_app_number] => 12/391764 [patent_app_country] => US [patent_app_date] => 2009-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 13547 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/639/07639548.pdf [firstpage_image] =>[orig_patent_app_number] => 12391764 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/391764
Semiconductor device having variable parameter selection based on temperature and test method Feb 23, 2009 Issued
Array ( [id] => 66476 [patent_doc_number] => 07760567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-20 [patent_title] => 'Semiconductor memory and system' [patent_app_type] => utility [patent_app_number] => 12/234181 [patent_app_country] => US [patent_app_date] => 2008-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12334 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/760/07760567.pdf [firstpage_image] =>[orig_patent_app_number] => 12234181 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/234181
Semiconductor memory and system Sep 18, 2008 Issued
Array ( [id] => 6218916 [patent_doc_number] => 20100054011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-04 [patent_title] => 'High speed SRAM' [patent_app_type] => utility [patent_app_number] => 12/202263 [patent_app_country] => US [patent_app_date] => 2008-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 15481 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20100054011.pdf [firstpage_image] =>[orig_patent_app_number] => 12202263 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/202263
High speed SRAM Aug 29, 2008 Issued
Array ( [id] => 5427247 [patent_doc_number] => 20090086557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/164637 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3520 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20090086557.pdf [firstpage_image] =>[orig_patent_app_number] => 12164637 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/164637
Synchronous semiconductor memory device and method for driving the same Jun 29, 2008 Issued
Array ( [id] => 105246 [patent_doc_number] => 07724575 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'Page-buffer and non-volatile semiconductor memory including page buffer' [patent_app_type] => utility [patent_app_number] => 12/035028 [patent_app_country] => US [patent_app_date] => 2008-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 15924 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/724/07724575.pdf [firstpage_image] =>[orig_patent_app_number] => 12035028 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/035028
Page-buffer and non-volatile semiconductor memory including page buffer Feb 20, 2008 Issued
Array ( [id] => 204597 [patent_doc_number] => 07633803 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-15 [patent_title] => 'Methods of operating memory devices including negative incremental step pulse programming and related devices' [patent_app_type] => utility [patent_app_number] => 12/021805 [patent_app_country] => US [patent_app_date] => 2008-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 12019 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/633/07633803.pdf [firstpage_image] =>[orig_patent_app_number] => 12021805 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/021805
Methods of operating memory devices including negative incremental step pulse programming and related devices Jan 28, 2008 Issued
Array ( [id] => 4833185 [patent_doc_number] => 20080131732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'MAGNETORESISTIVE ELEMENT' [patent_app_type] => utility [patent_app_number] => 12/019743 [patent_app_country] => US [patent_app_date] => 2008-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 65 [patent_figures_cnt] => 65 [patent_no_of_words] => 28102 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20080131732.pdf [firstpage_image] =>[orig_patent_app_number] => 12019743 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/019743
Magnetoresistive element Jan 24, 2008 Issued
Array ( [id] => 240555 [patent_doc_number] => 07593277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-22 [patent_title] => 'Method for compensated sensing in non-volatile memory' [patent_app_type] => utility [patent_app_number] => 12/020449 [patent_app_country] => US [patent_app_date] => 2008-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 42 [patent_no_of_words] => 24265 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/593/07593277.pdf [firstpage_image] =>[orig_patent_app_number] => 12020449 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/020449
Method for compensated sensing in non-volatile memory Jan 24, 2008 Issued
Array ( [id] => 5433895 [patent_doc_number] => 20090168481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'Tree-structure memory device' [patent_app_type] => utility [patent_app_number] => 12/006439 [patent_app_country] => US [patent_app_date] => 2007-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 17461 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20090168481.pdf [firstpage_image] =>[orig_patent_app_number] => 12006439 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/006439
Tree-structure memory device Dec 30, 2007 Issued
Array ( [id] => 45013 [patent_doc_number] => 07782684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Semiconductor memory device operating in a test mode and method for driving the same' [patent_app_type] => utility [patent_app_number] => 11/987829 [patent_app_country] => US [patent_app_date] => 2007-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5533 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/782/07782684.pdf [firstpage_image] =>[orig_patent_app_number] => 11987829 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/987829
Semiconductor memory device operating in a test mode and method for driving the same Dec 4, 2007 Issued
Array ( [id] => 85826 [patent_doc_number] => 07742356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-22 [patent_title] => 'Semiconductor memory device having a refresh cycle changing circuit' [patent_app_type] => utility [patent_app_number] => 11/987767 [patent_app_country] => US [patent_app_date] => 2007-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6482 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/742/07742356.pdf [firstpage_image] =>[orig_patent_app_number] => 11987767 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/987767
Semiconductor memory device having a refresh cycle changing circuit Dec 3, 2007 Issued
Array ( [id] => 218143 [patent_doc_number] => 07613053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-03 [patent_title] => 'Memory device and method of operating such a memory device' [patent_app_type] => utility [patent_app_number] => 11/984885 [patent_app_country] => US [patent_app_date] => 2007-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8415 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/613/07613053.pdf [firstpage_image] =>[orig_patent_app_number] => 11984885 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/984885
Memory device and method of operating such a memory device Nov 22, 2007 Issued
Array ( [id] => 331533 [patent_doc_number] => 07512033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-31 [patent_title] => 'Apparatus and method for controlling clock signal in semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/984007 [patent_app_country] => US [patent_app_date] => 2007-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 2774 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/512/07512033.pdf [firstpage_image] =>[orig_patent_app_number] => 11984007 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/984007
Apparatus and method for controlling clock signal in semiconductor memory device Nov 12, 2007 Issued
Array ( [id] => 218139 [patent_doc_number] => 07613052 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-03 [patent_title] => 'Memory device and method of operating such a memory device' [patent_app_type] => utility [patent_app_number] => 11/979359 [patent_app_country] => US [patent_app_date] => 2007-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12128 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/613/07613052.pdf [firstpage_image] =>[orig_patent_app_number] => 11979359 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/979359
Memory device and method of operating such a memory device Oct 31, 2007 Issued
Array ( [id] => 257374 [patent_doc_number] => 07577054 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-18 [patent_title] => 'Memory with word-line driver circuit having leakage prevention transistor' [patent_app_type] => utility [patent_app_number] => 11/979237 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6675 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/577/07577054.pdf [firstpage_image] =>[orig_patent_app_number] => 11979237 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/979237
Memory with word-line driver circuit having leakage prevention transistor Oct 30, 2007 Issued
Array ( [id] => 5329294 [patent_doc_number] => 20090109771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'Optimizing mode register set commands' [patent_app_type] => utility [patent_app_number] => 11/978811 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2768 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20090109771.pdf [firstpage_image] =>[orig_patent_app_number] => 11978811 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/978811
Optimizing mode register set commands Oct 29, 2007 Issued
Array ( [id] => 55612 [patent_doc_number] => 07773447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-10 [patent_title] => 'Memory circuit, semiconductor device and read control method of memory circuit' [patent_app_type] => utility [patent_app_number] => 11/976853 [patent_app_country] => US [patent_app_date] => 2007-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 9790 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/773/07773447.pdf [firstpage_image] =>[orig_patent_app_number] => 11976853 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/976853
Memory circuit, semiconductor device and read control method of memory circuit Oct 28, 2007 Issued
Array ( [id] => 209601 [patent_doc_number] => RE040995 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2009-11-24 [patent_title] => 'Multi-element resistive memory' [patent_app_type] => reissue [patent_app_number] => 11/905752 [patent_app_country] => US [patent_app_date] => 2007-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5610 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/040/RE040995.pdf [firstpage_image] =>[orig_patent_app_number] => 11905752 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/905752
Multi-element resistive memory Oct 2, 2007 Issued
Array ( [id] => 4908685 [patent_doc_number] => 20080019451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-24 [patent_title] => 'CIRCUITS AND METHODS FOR DATA BUS INVERSION IN A SEMICONDUCTOR MEMORY' [patent_app_type] => utility [patent_app_number] => 11/863604 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14353 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20080019451.pdf [firstpage_image] =>[orig_patent_app_number] => 11863604 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/863604
Circuits and methods for data bus inversion in a semiconductor memory Sep 27, 2007 Issued
Array ( [id] => 84248 [patent_doc_number] => 07746717 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-29 [patent_title] => 'Desensitizing static random access memory (SRAM) to process variation' [patent_app_type] => utility [patent_app_number] => 11/899825 [patent_app_country] => US [patent_app_date] => 2007-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5229 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/746/07746717.pdf [firstpage_image] =>[orig_patent_app_number] => 11899825 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/899825
Desensitizing static random access memory (SRAM) to process variation Sep 6, 2007 Issued
Menu