D Margaret M Seaman
Examiner (ID: 9100, Phone: (571)272-0694 , Office: P/1625 )
Most Active Art Unit | 1625 |
Art Unit(s) | 1612, 1621, 1625, 1203 |
Total Applications | 3010 |
Issued Applications | 2200 |
Pending Applications | 275 |
Abandoned Applications | 535 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 684182
[patent_doc_number] => 07082051
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-07-25
[patent_title] => 'Method and driver for programming phase change memory cell'
[patent_app_type] => utility
[patent_app_number] => 10/845065
[patent_app_country] => US
[patent_app_date] => 2004-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 7430
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/082/07082051.pdf
[firstpage_image] =>[orig_patent_app_number] => 10845065
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/845065 | Method and driver for programming phase change memory cell | May 13, 2004 | Issued |
Array
(
[id] => 644167
[patent_doc_number] => 07123540
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-10-17
[patent_title] => 'Semiconductor device having delay-locked loop and test method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/836333
[patent_app_country] => US
[patent_app_date] => 2004-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3057
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/123/07123540.pdf
[firstpage_image] =>[orig_patent_app_number] => 10836333
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/836333 | Semiconductor device having delay-locked loop and test method thereof | May 2, 2004 | Issued |
Array
(
[id] => 478671
[patent_doc_number] => 07227804
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-06-05
[patent_title] => 'Current source architecture for memory device standby current reduction'
[patent_app_type] => utility
[patent_app_number] => 10/827785
[patent_app_country] => US
[patent_app_date] => 2004-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 5606
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/227/07227804.pdf
[firstpage_image] =>[orig_patent_app_number] => 10827785
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/827785 | Current source architecture for memory device standby current reduction | Apr 18, 2004 | Issued |
Array
(
[id] => 7415584
[patent_doc_number] => 20040264268
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-30
[patent_title] => 'Erroneous operation preventing circuit of non-volatile memory device'
[patent_app_type] => new
[patent_app_number] => 10/824831
[patent_app_country] => US
[patent_app_date] => 2004-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8108
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0264/20040264268.pdf
[firstpage_image] =>[orig_patent_app_number] => 10824831
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/824831 | Erroneous operation preventing circuit of non-volatile memory device | Apr 13, 2004 | Issued |
Array
(
[id] => 6950941
[patent_doc_number] => 20050226035
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-13
[patent_title] => 'Multi-cell resistive memory array architecture with select transistor'
[patent_app_type] => utility
[patent_app_number] => 10/822785
[patent_app_country] => US
[patent_app_date] => 2004-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5578
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0226/20050226035.pdf
[firstpage_image] =>[orig_patent_app_number] => 10822785
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/822785 | Multi-cell resistive memory array architecture with select transistor | Apr 12, 2004 | Issued |
Array
(
[id] => 7419030
[patent_doc_number] => 20040208071
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-21
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => new
[patent_app_number] => 10/821983
[patent_app_country] => US
[patent_app_date] => 2004-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 13543
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0208/20040208071.pdf
[firstpage_image] =>[orig_patent_app_number] => 10821983
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/821983 | Semiconductor memory device | Apr 11, 2004 | Issued |
Array
(
[id] => 636024
[patent_doc_number] => 07130240
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-10-31
[patent_title] => 'Semiconductor memory system and method for multi-sector erase operation'
[patent_app_type] => utility
[patent_app_number] => 10/822167
[patent_app_country] => US
[patent_app_date] => 2004-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 5285
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 26
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/130/07130240.pdf
[firstpage_image] =>[orig_patent_app_number] => 10822167
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/822167 | Semiconductor memory system and method for multi-sector erase operation | Apr 7, 2004 | Issued |
Array
(
[id] => 7180099
[patent_doc_number] => 20050190592
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-01
[patent_title] => 'Memory unit and memory module using the same'
[patent_app_type] => utility
[patent_app_number] => 10/791341
[patent_app_country] => US
[patent_app_date] => 2004-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2483
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0190/20050190592.pdf
[firstpage_image] =>[orig_patent_app_number] => 10791341
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/791341 | Memory unit and memory module using the same | Feb 29, 2004 | Issued |
Array
(
[id] => 6982108
[patent_doc_number] => 20050152177
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-14
[patent_title] => 'Tamper memory cell'
[patent_app_type] => utility
[patent_app_number] => 10/783935
[patent_app_country] => US
[patent_app_date] => 2004-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3857
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0152/20050152177.pdf
[firstpage_image] =>[orig_patent_app_number] => 10783935
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/783935 | Tamper memory cell | Feb 19, 2004 | Issued |
Array
(
[id] => 7418818
[patent_doc_number] => 20040208046
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-21
[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => new
[patent_app_number] => 10/778320
[patent_app_country] => US
[patent_app_date] => 2004-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 11671
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0208/20040208046.pdf
[firstpage_image] =>[orig_patent_app_number] => 10778320
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/778320 | Semiconductor integrated circuit | Feb 16, 2004 | Issued |
Array
(
[id] => 7134684
[patent_doc_number] => 20050180214
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-18
[patent_title] => 'Technique for programming floating-gate transistor used in circuitry as flash EPROM'
[patent_app_type] => utility
[patent_app_number] => 10/780031
[patent_app_country] => US
[patent_app_date] => 2004-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 13843
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0180/20050180214.pdf
[firstpage_image] =>[orig_patent_app_number] => 10780031
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/780031 | Technique for programming floating-gate transistor used in circuitry as flash EPROM | Feb 16, 2004 | Issued |
Array
(
[id] => 657251
[patent_doc_number] => 07110287
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-19
[patent_title] => 'Method and system for providing heat assisted switching of a magnetic element utilizing spin transfer'
[patent_app_type] => utility
[patent_app_number] => 10/778735
[patent_app_country] => US
[patent_app_date] => 2004-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 10796
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 18
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/110/07110287.pdf
[firstpage_image] =>[orig_patent_app_number] => 10778735
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/778735 | Method and system for providing heat assisted switching of a magnetic element utilizing spin transfer | Feb 12, 2004 | Issued |
Array
(
[id] => 682471
[patent_doc_number] => 07085155
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-01
[patent_title] => 'Secured phase-change devices'
[patent_app_type] => utility
[patent_app_number] => 10/775431
[patent_app_country] => US
[patent_app_date] => 2004-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 9168
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/085/07085155.pdf
[firstpage_image] =>[orig_patent_app_number] => 10775431
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/775431 | Secured phase-change devices | Feb 9, 2004 | Issued |
Array
(
[id] => 7225371
[patent_doc_number] => 20040156230
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-12
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => new
[patent_app_number] => 10/772323
[patent_app_country] => US
[patent_app_date] => 2004-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7887
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0156/20040156230.pdf
[firstpage_image] =>[orig_patent_app_number] => 10772323
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/772323 | Semiconductor memory device | Feb 5, 2004 | Issued |
Array
(
[id] => 503309
[patent_doc_number] => 07209389
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-24
[patent_title] => 'Trap read only non-volatile memory (TROM)'
[patent_app_type] => utility
[patent_app_number] => 10/771023
[patent_app_country] => US
[patent_app_date] => 2004-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 4583
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/209/07209389.pdf
[firstpage_image] =>[orig_patent_app_number] => 10771023
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/771023 | Trap read only non-volatile memory (TROM) | Feb 2, 2004 | Issued |
Array
(
[id] => 762105
[patent_doc_number] => 07016245
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-03-21
[patent_title] => 'Tracking circuit enabling quick/accurate retrieval of data stored in a memory array'
[patent_app_type] => utility
[patent_app_number] => 10/768131
[patent_app_country] => US
[patent_app_date] => 2004-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 6303
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 322
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/016/07016245.pdf
[firstpage_image] =>[orig_patent_app_number] => 10768131
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/768131 | Tracking circuit enabling quick/accurate retrieval of data stored in a memory array | Feb 1, 2004 | Issued |
Array
(
[id] => 490158
[patent_doc_number] => 07218565
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-05-15
[patent_title] => 'Method and apparatus for independently refreshing memory capacitors'
[patent_app_type] => utility
[patent_app_number] => 10/707652
[patent_app_country] => US
[patent_app_date] => 2003-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 3085
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/218/07218565.pdf
[firstpage_image] =>[orig_patent_app_number] => 10707652
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/707652 | Method and apparatus for independently refreshing memory capacitors | Dec 29, 2003 | Issued |
Array
(
[id] => 426305
[patent_doc_number] => 07272065
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-09-18
[patent_title] => 'Compensated refresh oscillator'
[patent_app_type] => utility
[patent_app_number] => 10/726439
[patent_app_country] => US
[patent_app_date] => 2003-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5664
[patent_no_of_claims] => 56
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 40
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/272/07272065.pdf
[firstpage_image] =>[orig_patent_app_number] => 10726439
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/726439 | Compensated refresh oscillator | Dec 2, 2003 | Issued |
Array
(
[id] => 512267
[patent_doc_number] => 07203118
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-10
[patent_title] => 'Semiconductor storage device and mobile electronic device'
[patent_app_type] => utility
[patent_app_number] => 10/528997
[patent_app_country] => US
[patent_app_date] => 2003-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 30
[patent_no_of_words] => 22366
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/203/07203118.pdf
[firstpage_image] =>[orig_patent_app_number] => 10528997
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/528997 | Semiconductor storage device and mobile electronic device | Sep 9, 2003 | Issued |
Array
(
[id] => 544962
[patent_doc_number] => 07173840
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-06
[patent_title] => 'Acceleration of the programming of a memory module with the aid of a boundary scan (BSCAN) register'
[patent_app_type] => utility
[patent_app_number] => 10/529331
[patent_app_country] => US
[patent_app_date] => 2003-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3341
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/173/07173840.pdf
[firstpage_image] =>[orig_patent_app_number] => 10529331
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/529331 | Acceleration of the programming of a memory module with the aid of a boundary scan (BSCAN) register | Sep 2, 2003 | Issued |