Search

D Margaret M Seaman

Examiner (ID: 9100, Phone: (571)272-0694 , Office: P/1625 )

Most Active Art Unit
1625
Art Unit(s)
1612, 1621, 1625, 1203
Total Applications
3010
Issued Applications
2200
Pending Applications
275
Abandoned Applications
535

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 179025 [patent_doc_number] => 07656736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-02 [patent_title] => 'Semiconductor device including internal voltage generation circuit' [patent_app_type] => utility [patent_app_number] => 11/717717 [patent_app_country] => US [patent_app_date] => 2007-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 29 [patent_no_of_words] => 11120 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/656/07656736.pdf [firstpage_image] =>[orig_patent_app_number] => 11717717 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/717717
Semiconductor device including internal voltage generation circuit Mar 13, 2007 Issued
Array ( [id] => 186841 [patent_doc_number] => 07649801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-19 [patent_title] => 'Semiconductor memory apparatus having column decoder for low power consumption' [patent_app_type] => utility [patent_app_number] => 11/716635 [patent_app_country] => US [patent_app_date] => 2007-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2814 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/649/07649801.pdf [firstpage_image] =>[orig_patent_app_number] => 11716635 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/716635
Semiconductor memory apparatus having column decoder for low power consumption Mar 11, 2007 Issued
Array ( [id] => 4931677 [patent_doc_number] => 20080002452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'Method for setting a read voltage, and semiconductor circuit arrangement' [patent_app_type] => utility [patent_app_number] => 11/716381 [patent_app_country] => US [patent_app_date] => 2007-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6298 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20080002452.pdf [firstpage_image] =>[orig_patent_app_number] => 11716381 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/716381
Method for setting a read voltage, and semiconductor circuit arrangement Mar 8, 2007 Abandoned
Array ( [id] => 198912 [patent_doc_number] => 07639557 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-12-29 [patent_title] => 'Configurable random-access-memory circuitry' [patent_app_type] => utility [patent_app_number] => 11/714327 [patent_app_country] => US [patent_app_date] => 2007-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8157 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/639/07639557.pdf [firstpage_image] =>[orig_patent_app_number] => 11714327 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/714327
Configurable random-access-memory circuitry Mar 4, 2007 Issued
Array ( [id] => 257379 [patent_doc_number] => 07577059 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-18 [patent_title] => 'Decoding control with address transition detection in page erase function' [patent_app_type] => utility [patent_app_number] => 11/711043 [patent_app_country] => US [patent_app_date] => 2007-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/577/07577059.pdf [firstpage_image] =>[orig_patent_app_number] => 11711043 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/711043
Decoding control with address transition detection in page erase function Feb 26, 2007 Issued
Array ( [id] => 4725630 [patent_doc_number] => 20080205171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'Redundant cross point switching system and method' [patent_app_type] => utility [patent_app_number] => 11/711243 [patent_app_country] => US [patent_app_date] => 2007-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4430 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20080205171.pdf [firstpage_image] =>[orig_patent_app_number] => 11711243 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/711243
Redundant cross point switching system and method Feb 26, 2007 Issued
Array ( [id] => 4725641 [patent_doc_number] => 20080205182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'Method of operating a memory cell, memory cell and memory unit' [patent_app_type] => utility [patent_app_number] => 11/710859 [patent_app_country] => US [patent_app_date] => 2007-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6562 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20080205182.pdf [firstpage_image] =>[orig_patent_app_number] => 11710859 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/710859
Method of operating a memory cell, memory cell and memory unit Feb 25, 2007 Issued
Array ( [id] => 4878287 [patent_doc_number] => 20080151670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'Memory device, memory controller and memory system' [patent_app_type] => utility [patent_app_number] => 11/709867 [patent_app_country] => US [patent_app_date] => 2007-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 183 [patent_figures_cnt] => 183 [patent_no_of_words] => 76685 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11709867 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/709867
Memory device, memory controller and memory system Feb 22, 2007 Abandoned
Array ( [id] => 834753 [patent_doc_number] => 07397683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-08 [patent_title] => 'Associative memory having a mask function for use in a network router' [patent_app_type] => utility [patent_app_number] => 11/677153 [patent_app_country] => US [patent_app_date] => 2007-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 22109 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/397/07397683.pdf [firstpage_image] =>[orig_patent_app_number] => 11677153 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/677153
Associative memory having a mask function for use in a network router Feb 20, 2007 Issued
Array ( [id] => 304639 [patent_doc_number] => 07535786 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-05-19 [patent_title] => 'Semiconductor device having variable parameter selection based on temperature and test method' [patent_app_type] => utility [patent_app_number] => 11/708185 [patent_app_country] => US [patent_app_date] => 2007-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 13503 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/535/07535786.pdf [firstpage_image] =>[orig_patent_app_number] => 11708185 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/708185
Semiconductor device having variable parameter selection based on temperature and test method Feb 19, 2007 Issued
Array ( [id] => 5111663 [patent_doc_number] => 20070195578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/707157 [patent_app_country] => US [patent_app_date] => 2007-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7467 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20070195578.pdf [firstpage_image] =>[orig_patent_app_number] => 11707157 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/707157
Semiconductor memory device Feb 15, 2007 Abandoned
Array ( [id] => 4847597 [patent_doc_number] => 20080184005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'METHODS AND APPARATUS FOR USING A CONFIGURATION ARRAY SIMILAR TO AN ASSOCIATED DATA ARRAY' [patent_app_type] => utility [patent_app_number] => 11/669923 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4594 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20080184005.pdf [firstpage_image] =>[orig_patent_app_number] => 11669923 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/669923
Methods and apparatus for using a configuration array similar to an associated data array Jan 30, 2007 Issued
Array ( [id] => 374275 [patent_doc_number] => 07474581 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Memory synchronization method and refresh control circuit' [patent_app_type] => utility [patent_app_number] => 11/698165 [patent_app_country] => US [patent_app_date] => 2007-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 4495 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/474/07474581.pdf [firstpage_image] =>[orig_patent_app_number] => 11698165 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/698165
Memory synchronization method and refresh control circuit Jan 25, 2007 Issued
Array ( [id] => 4844632 [patent_doc_number] => 20080181040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'N-port memory circuits allowing M memory addresses to be accessed concurrently and signal processing methods thereof' [patent_app_type] => utility [patent_app_number] => 11/699309 [patent_app_country] => US [patent_app_date] => 2007-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2947 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20080181040.pdf [firstpage_image] =>[orig_patent_app_number] => 11699309 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/699309
N-port memory circuits allowing M memory addresses to be accessed concurrently and signal processing methods thereof Jan 25, 2007 Issued
Array ( [id] => 5176368 [patent_doc_number] => 20070177427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'Nonvolatile memory device and method thereof' [patent_app_type] => utility [patent_app_number] => 11/698071 [patent_app_country] => US [patent_app_date] => 2007-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5431 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20070177427.pdf [firstpage_image] =>[orig_patent_app_number] => 11698071 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/698071
Nonvolatile memory device and method thereof Jan 25, 2007 Abandoned
Array ( [id] => 4844627 [patent_doc_number] => 20080181035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'Method and system for a dynamically repairable memory' [patent_app_type] => utility [patent_app_number] => 11/698681 [patent_app_country] => US [patent_app_date] => 2007-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4195 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20080181035.pdf [firstpage_image] =>[orig_patent_app_number] => 11698681 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/698681
Method and system for a dynamically repairable memory Jan 25, 2007 Abandoned
Array ( [id] => 5094135 [patent_doc_number] => 20070115744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'Register Read for Volatile Memory' [patent_app_type] => utility [patent_app_number] => 11/623349 [patent_app_country] => US [patent_app_date] => 2007-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3504 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20070115744.pdf [firstpage_image] =>[orig_patent_app_number] => 11623349 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/623349
Register read for volatile memory Jan 15, 2007 Issued
Array ( [id] => 4878265 [patent_doc_number] => 20080151648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'High speed fanned out system architecture and input/output circuits for non-volatile memory' [patent_app_type] => utility [patent_app_number] => 11/645043 [patent_app_country] => US [patent_app_date] => 2006-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2984 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20080151648.pdf [firstpage_image] =>[orig_patent_app_number] => 11645043 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/645043
High speed fanned out system architecture and input/output circuits for non-volatile memory Dec 20, 2006 Issued
Array ( [id] => 854778 [patent_doc_number] => 07379370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-27 [patent_title] => 'Semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/641767 [patent_app_country] => US [patent_app_date] => 2006-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 20414 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/379/07379370.pdf [firstpage_image] =>[orig_patent_app_number] => 11641767 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/641767
Semiconductor memory Dec 19, 2006 Issued
Array ( [id] => 4865289 [patent_doc_number] => 20080144348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'HIGH PERFORMANCE SINGLE EVENT UPSET HARDENED SRAM CELL' [patent_app_type] => utility [patent_app_number] => 11/612809 [patent_app_country] => US [patent_app_date] => 2006-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1543 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20080144348.pdf [firstpage_image] =>[orig_patent_app_number] => 11612809 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/612809
High performance single event upset hardened SRAM cell Dec 18, 2006 Issued
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