Search

D Margaret M Seaman

Examiner (ID: 9100, Phone: (571)272-0694 , Office: P/1625 )

Most Active Art Unit
1625
Art Unit(s)
1612, 1621, 1625, 1203
Total Applications
3010
Issued Applications
2200
Pending Applications
275
Abandoned Applications
535

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4865337 [patent_doc_number] => 20080144396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'ERASING FLASH MEMORY USING ADAPTIVE DRAIN AND/OR GATE BIAS' [patent_app_type] => utility [patent_app_number] => 11/612863 [patent_app_country] => US [patent_app_date] => 2006-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6181 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20080144396.pdf [firstpage_image] =>[orig_patent_app_number] => 11612863 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/612863
Erasing flash memory using adaptive drain and/or gate bias Dec 18, 2006 Issued
Array ( [id] => 4865316 [patent_doc_number] => 20080144375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'FLASH MEMORY DEVICE WITH SHUNT' [patent_app_type] => utility [patent_app_number] => 11/613175 [patent_app_country] => US [patent_app_date] => 2006-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1791 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20080144375.pdf [firstpage_image] =>[orig_patent_app_number] => 11613175 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/613175
Flash memory device with shunt Dec 18, 2006 Issued
Array ( [id] => 5233946 [patent_doc_number] => 20070126101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-07 [patent_title] => 'Memory card module' [patent_app_type] => utility [patent_app_number] => 11/633423 [patent_app_country] => US [patent_app_date] => 2006-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1996 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20070126101.pdf [firstpage_image] =>[orig_patent_app_number] => 11633423 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/633423
Memory card module Dec 4, 2006 Issued
Array ( [id] => 7592256 [patent_doc_number] => 07652949 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-26 [patent_title] => 'Memory module and register with minimized routing path' [patent_app_type] => utility [patent_app_number] => 11/633353 [patent_app_country] => US [patent_app_date] => 2006-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7304 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/652/07652949.pdf [firstpage_image] =>[orig_patent_app_number] => 11633353 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/633353
Memory module and register with minimized routing path Dec 3, 2006 Issued
Array ( [id] => 364849 [patent_doc_number] => 07483310 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-01-27 [patent_title] => 'System and method for providing high endurance low cost CMOS compatible EEPROM devices' [patent_app_type] => utility [patent_app_number] => 11/591853 [patent_app_country] => US [patent_app_date] => 2006-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 9934 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/483/07483310.pdf [firstpage_image] =>[orig_patent_app_number] => 11591853 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/591853
System and method for providing high endurance low cost CMOS compatible EEPROM devices Nov 1, 2006 Issued
Array ( [id] => 253672 [patent_doc_number] => 07580313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-25 [patent_title] => 'Semiconductor memory device for reducing cell area' [patent_app_type] => utility [patent_app_number] => 11/589038 [patent_app_country] => US [patent_app_date] => 2006-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3378 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/580/07580313.pdf [firstpage_image] =>[orig_patent_app_number] => 11589038 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/589038
Semiconductor memory device for reducing cell area Oct 29, 2006 Issued
Array ( [id] => 4892046 [patent_doc_number] => 20080101143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'MEMORY DEVICE WITH CONFIGURABLE DELAY TRACKING' [patent_app_type] => utility [patent_app_number] => 11/552893 [patent_app_country] => US [patent_app_date] => 2006-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6373 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20080101143.pdf [firstpage_image] =>[orig_patent_app_number] => 11552893 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/552893
Memory device with configurable delay tracking Oct 24, 2006 Issued
Array ( [id] => 218134 [patent_doc_number] => 07613047 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-03 [patent_title] => 'Efficient circuit and method to measure resistance thresholds' [patent_app_type] => utility [patent_app_number] => 11/538945 [patent_app_country] => US [patent_app_date] => 2006-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3378 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/613/07613047.pdf [firstpage_image] =>[orig_patent_app_number] => 11538945 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/538945
Efficient circuit and method to measure resistance thresholds Oct 4, 2006 Issued
Array ( [id] => 804691 [patent_doc_number] => 07423904 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-09 [patent_title] => 'Non-volatile semiconductor memory device and operating method thereof' [patent_app_type] => utility [patent_app_number] => 11/538689 [patent_app_country] => US [patent_app_date] => 2006-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5908 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/423/07423904.pdf [firstpage_image] =>[orig_patent_app_number] => 11538689 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/538689
Non-volatile semiconductor memory device and operating method thereof Oct 3, 2006 Issued
Array ( [id] => 286546 [patent_doc_number] => 07551476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-23 [patent_title] => 'Resistive memory having shunted memory cells' [patent_app_type] => utility [patent_app_number] => 11/541973 [patent_app_country] => US [patent_app_date] => 2006-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8720 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/551/07551476.pdf [firstpage_image] =>[orig_patent_app_number] => 11541973 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/541973
Resistive memory having shunted memory cells Oct 1, 2006 Issued
Array ( [id] => 5170366 [patent_doc_number] => 20070070797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Data transmission device in semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/529261 [patent_app_country] => US [patent_app_date] => 2006-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2528 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20070070797.pdf [firstpage_image] =>[orig_patent_app_number] => 11529261 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/529261
Data transmission device in semiconductor memory device Sep 28, 2006 Issued
Array ( [id] => 578591 [patent_doc_number] => 07466608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-16 [patent_title] => 'Data input/output circuit having data inversion determination function and semiconductor memory device having the same' [patent_app_type] => utility [patent_app_number] => 11/528799 [patent_app_country] => US [patent_app_date] => 2006-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5118 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/466/07466608.pdf [firstpage_image] =>[orig_patent_app_number] => 11528799 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/528799
Data input/output circuit having data inversion determination function and semiconductor memory device having the same Sep 27, 2006 Issued
Array ( [id] => 218166 [patent_doc_number] => 07613065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-03 [patent_title] => 'Multi-port memory device' [patent_app_type] => utility [patent_app_number] => 11/528671 [patent_app_country] => US [patent_app_date] => 2006-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 8154 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/613/07613065.pdf [firstpage_image] =>[orig_patent_app_number] => 11528671 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/528671
Multi-port memory device Sep 27, 2006 Issued
Array ( [id] => 225894 [patent_doc_number] => 07606082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-20 [patent_title] => 'Semiconductor circuit, inverter circuit, semiconductor apparatus, and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/532083 [patent_app_country] => US [patent_app_date] => 2006-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8674 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/606/07606082.pdf [firstpage_image] =>[orig_patent_app_number] => 11532083 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/532083
Semiconductor circuit, inverter circuit, semiconductor apparatus, and manufacturing method thereof Sep 13, 2006 Issued
Array ( [id] => 589124 [patent_doc_number] => 07453731 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-18 [patent_title] => 'Method for non-volatile memory with linear estimation of initial programming voltage' [patent_app_type] => utility [patent_app_number] => 11/531227 [patent_app_country] => US [patent_app_date] => 2006-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 11049 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/453/07453731.pdf [firstpage_image] =>[orig_patent_app_number] => 11531227 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/531227
Method for non-volatile memory with linear estimation of initial programming voltage Sep 11, 2006 Issued
Array ( [id] => 5140457 [patent_doc_number] => 20070002673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'Memory array leakage reduction circuit and method' [patent_app_type] => utility [patent_app_number] => 11/516209 [patent_app_country] => US [patent_app_date] => 2006-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5199 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20070002673.pdf [firstpage_image] =>[orig_patent_app_number] => 11516209 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/516209
Memory array leakage reduction circuit and method Sep 4, 2006 Issued
Array ( [id] => 5687101 [patent_doc_number] => 20060285416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'Circuit and method for reading an antifuse' [patent_app_type] => utility [patent_app_number] => 11/509955 [patent_app_country] => US [patent_app_date] => 2006-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6206 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20060285416.pdf [firstpage_image] =>[orig_patent_app_number] => 11509955 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/509955
Circuit and method for reading an antifuse Aug 24, 2006 Issued
Array ( [id] => 5687100 [patent_doc_number] => 20060285415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'Circuit and method for reading an antifuse' [patent_app_type] => utility [patent_app_number] => 11/509952 [patent_app_country] => US [patent_app_date] => 2006-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6204 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20060285415.pdf [firstpage_image] =>[orig_patent_app_number] => 11509952 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/509952
Circuit and method for reading an antifuse Aug 24, 2006 Issued
Array ( [id] => 419726 [patent_doc_number] => 07277349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-02 [patent_title] => 'Circuit and method for reading an antifuse' [patent_app_type] => utility [patent_app_number] => 11/509956 [patent_app_country] => US [patent_app_date] => 2006-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6222 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/277/07277349.pdf [firstpage_image] =>[orig_patent_app_number] => 11509956 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/509956
Circuit and method for reading an antifuse Aug 24, 2006 Issued
Array ( [id] => 4650051 [patent_doc_number] => 20080037307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'Non-volatile memory erase verify' [patent_app_type] => utility [patent_app_number] => 11/502317 [patent_app_country] => US [patent_app_date] => 2006-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3000 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20080037307.pdf [firstpage_image] =>[orig_patent_app_number] => 11502317 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/502317
Non-volatile memory erase verify Aug 8, 2006 Issued
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