Search

D Margaret M Seaman

Examiner (ID: 9100, Phone: (571)272-0694 , Office: P/1625 )

Most Active Art Unit
1625
Art Unit(s)
1612, 1621, 1625, 1203
Total Applications
3010
Issued Applications
2200
Pending Applications
275
Abandoned Applications
535

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5864368 [patent_doc_number] => 20060098498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Methods of reading data including comparing multiple measurements of a characteristic of a data storage element and related devices' [patent_app_type] => utility [patent_app_number] => 11/241605 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6681 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20060098498.pdf [firstpage_image] =>[orig_patent_app_number] => 11241605 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/241605
Methods of reading data including comparing multiple measurements of a characteristic of a data storage element and related devices Sep 29, 2005 Abandoned
Array ( [id] => 5840539 [patent_doc_number] => 20060120172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Page-buffer and non-volatile semiconductor memory including page buffer' [patent_app_type] => utility [patent_app_number] => 11/228189 [patent_app_country] => US [patent_app_date] => 2005-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 15909 [patent_no_of_claims] => 81 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20060120172.pdf [firstpage_image] =>[orig_patent_app_number] => 11228189 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/228189
Page-buffer and non-volatile semiconductor memory including page buffer Sep 18, 2005 Issued
Array ( [id] => 824481 [patent_doc_number] => 07405956 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-29 [patent_title] => 'Line layout structure of semiconductor memory devices' [patent_app_type] => utility [patent_app_number] => 11/227563 [patent_app_country] => US [patent_app_date] => 2005-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4677 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/405/07405956.pdf [firstpage_image] =>[orig_patent_app_number] => 11227563 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/227563
Line layout structure of semiconductor memory devices Sep 14, 2005 Issued
Array ( [id] => 5055549 [patent_doc_number] => 20070058470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Serial presence detect functionality on memory component' [patent_app_type] => utility [patent_app_number] => 11/227585 [patent_app_country] => US [patent_app_date] => 2005-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3358 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20070058470.pdf [firstpage_image] =>[orig_patent_app_number] => 11227585 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/227585
Serial presence detect functionality on memory component Sep 14, 2005 Issued
Array ( [id] => 5181893 [patent_doc_number] => 20070053236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-08 [patent_title] => 'Fuse resistance read-out circuit' [patent_app_type] => utility [patent_app_number] => 11/210055 [patent_app_country] => US [patent_app_date] => 2005-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3640 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20070053236.pdf [firstpage_image] =>[orig_patent_app_number] => 11210055 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/210055
Fuse resistance read-out circuit Aug 22, 2005 Issued
Array ( [id] => 5709200 [patent_doc_number] => 20060050545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-09 [patent_title] => 'Integrated memory arrangement based on resistive memory cells and production method' [patent_app_type] => utility [patent_app_number] => 11/209977 [patent_app_country] => US [patent_app_date] => 2005-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3199 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20060050545.pdf [firstpage_image] =>[orig_patent_app_number] => 11209977 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/209977
Integrated memory arrangement based on resistive memory cells and production method Aug 22, 2005 Issued
Array ( [id] => 459582 [patent_doc_number] => 07245519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-17 [patent_title] => 'Digitally programmable capacitor array' [patent_app_type] => utility [patent_app_number] => 11/209117 [patent_app_country] => US [patent_app_date] => 2005-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2471 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/245/07245519.pdf [firstpage_image] =>[orig_patent_app_number] => 11209117 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/209117
Digitally programmable capacitor array Aug 21, 2005 Issued
Array ( [id] => 7228429 [patent_doc_number] => 20050269626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-08 [patent_title] => 'Vertical NAND flash memory device' [patent_app_type] => utility [patent_app_number] => 11/190467 [patent_app_country] => US [patent_app_date] => 2005-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5065 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20050269626.pdf [firstpage_image] =>[orig_patent_app_number] => 11190467 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/190467
Vertical NAND flash memory device Jul 26, 2005 Issued
Array ( [id] => 380706 [patent_doc_number] => 07310283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-18 [patent_title] => 'Apparatus and method for controlling clock signal in semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/188715 [patent_app_country] => US [patent_app_date] => 2005-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 2721 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/310/07310283.pdf [firstpage_image] =>[orig_patent_app_number] => 11188715 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/188715
Apparatus and method for controlling clock signal in semiconductor memory device Jul 25, 2005 Issued
Array ( [id] => 5241004 [patent_doc_number] => 20070019495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Address decoding systems and methods' [patent_app_type] => utility [patent_app_number] => 11/187179 [patent_app_country] => US [patent_app_date] => 2005-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2974 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20070019495.pdf [firstpage_image] =>[orig_patent_app_number] => 11187179 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/187179
Address decoding systems and methods Jul 21, 2005 Issued
Array ( [id] => 5792366 [patent_doc_number] => 20060013047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-19 [patent_title] => 'Charge pump circuit' [patent_app_type] => utility [patent_app_number] => 11/174801 [patent_app_country] => US [patent_app_date] => 2005-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6257 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20060013047.pdf [firstpage_image] =>[orig_patent_app_number] => 11174801 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/174801
Charge pump circuit Jul 4, 2005 Issued
Array ( [id] => 503174 [patent_doc_number] => 07209377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-24 [patent_title] => 'Ferroelectric memory device, electronic device' [patent_app_type] => utility [patent_app_number] => 11/174905 [patent_app_country] => US [patent_app_date] => 2005-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3947 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/209/07209377.pdf [firstpage_image] =>[orig_patent_app_number] => 11174905 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/174905
Ferroelectric memory device, electronic device Jul 4, 2005 Issued
Array ( [id] => 490152 [patent_doc_number] => 07218562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-15 [patent_title] => 'Recovering bit lines in a memory array after stopped clock operation' [patent_app_type] => utility [patent_app_number] => 11/173119 [patent_app_country] => US [patent_app_date] => 2005-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4897 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/218/07218562.pdf [firstpage_image] =>[orig_patent_app_number] => 11173119 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/173119
Recovering bit lines in a memory array after stopped clock operation Jun 30, 2005 Issued
Array ( [id] => 5618208 [patent_doc_number] => 20060187741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Method and apparatus for avoiding bi-directional signal fighting of serial interface' [patent_app_type] => utility [patent_app_number] => 11/158409 [patent_app_country] => US [patent_app_date] => 2005-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2116 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20060187741.pdf [firstpage_image] =>[orig_patent_app_number] => 11158409 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/158409
Method and apparatus for avoiding bi-directional signal fighting of serial interface Jun 20, 2005 Issued
Array ( [id] => 517074 [patent_doc_number] => 07200028 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-03 [patent_title] => 'Ferroelectric memory device and its driving method' [patent_app_type] => utility [patent_app_number] => 11/157519 [patent_app_country] => US [patent_app_date] => 2005-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10013 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/200/07200028.pdf [firstpage_image] =>[orig_patent_app_number] => 11157519 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/157519
Ferroelectric memory device and its driving method Jun 20, 2005 Issued
Array ( [id] => 5752553 [patent_doc_number] => 20060221702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'Decoding circuit for non-binary groups of memory line drivers' [patent_app_type] => utility [patent_app_number] => 11/146952 [patent_app_country] => US [patent_app_date] => 2005-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9575 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20060221702.pdf [firstpage_image] =>[orig_patent_app_number] => 11146952 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/146952
Decoding circuit for non-binary groups of memory line drivers Jun 6, 2005 Issued
Array ( [id] => 507490 [patent_doc_number] => 07206252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-17 [patent_title] => 'Circuit and method for generating word line control signals and semiconductor memory device having the same' [patent_app_type] => utility [patent_app_number] => 11/141783 [patent_app_country] => US [patent_app_date] => 2005-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 5576 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/206/07206252.pdf [firstpage_image] =>[orig_patent_app_number] => 11141783 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/141783
Circuit and method for generating word line control signals and semiconductor memory device having the same May 30, 2005 Issued
Array ( [id] => 308454 [patent_doc_number] => 07532532 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-12 [patent_title] => 'System and method for hidden-refresh rate modification' [patent_app_type] => utility [patent_app_number] => 11/140791 [patent_app_country] => US [patent_app_date] => 2005-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7286 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/532/07532532.pdf [firstpage_image] =>[orig_patent_app_number] => 11140791 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/140791
System and method for hidden-refresh rate modification May 30, 2005 Issued
Array ( [id] => 754375 [patent_doc_number] => 07023761 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-04 [patent_title] => 'Programmable stackable memory array system' [patent_app_type] => utility [patent_app_number] => 11/134173 [patent_app_country] => US [patent_app_date] => 2005-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 5302 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/023/07023761.pdf [firstpage_image] =>[orig_patent_app_number] => 11134173 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/134173
Programmable stackable memory array system May 19, 2005 Issued
Array ( [id] => 391225 [patent_doc_number] => 07301822 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-11-27 [patent_title] => 'Multi-boot configuration of programmable devices' [patent_app_type] => utility [patent_app_number] => 11/131751 [patent_app_country] => US [patent_app_date] => 2005-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8167 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/301/07301822.pdf [firstpage_image] =>[orig_patent_app_number] => 11131751 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/131751
Multi-boot configuration of programmable devices May 17, 2005 Issued
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