Search

D Margaret M Seaman

Examiner (ID: 9100, Phone: (571)272-0694 , Office: P/1625 )

Most Active Art Unit
1625
Art Unit(s)
1612, 1621, 1625, 1203
Total Applications
3010
Issued Applications
2200
Pending Applications
275
Abandoned Applications
535

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 475585 [patent_doc_number] => 07230876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-12 [patent_title] => 'Register read for volatile memory' [patent_app_type] => utility [patent_app_number] => 11/128829 [patent_app_country] => US [patent_app_date] => 2005-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3492 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/230/07230876.pdf [firstpage_image] =>[orig_patent_app_number] => 11128829 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/128829
Register read for volatile memory May 12, 2005 Issued
Array ( [id] => 416690 [patent_doc_number] => 07280413 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-09 [patent_title] => 'Nonvolatile semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/124253 [patent_app_country] => US [patent_app_date] => 2005-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5371 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/280/07280413.pdf [firstpage_image] =>[orig_patent_app_number] => 11124253 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/124253
Nonvolatile semiconductor memory May 8, 2005 Issued
Array ( [id] => 5833416 [patent_doc_number] => 20060245246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Inversion bit line, charge trapping non-volatile memory and method of operating same' [patent_app_type] => utility [patent_app_number] => 11/118839 [patent_app_country] => US [patent_app_date] => 2005-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6091 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20060245246.pdf [firstpage_image] =>[orig_patent_app_number] => 11118839 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/118839
Inversion bit line, charge trapping non-volatile memory and method of operating same Apr 28, 2005 Issued
Array ( [id] => 569105 [patent_doc_number] => 07161860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-09 [patent_title] => 'Local input/output line precharge circuit of semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/115373 [patent_app_country] => US [patent_app_date] => 2005-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3837 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/161/07161860.pdf [firstpage_image] =>[orig_patent_app_number] => 11115373 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/115373
Local input/output line precharge circuit of semiconductor memory device Apr 26, 2005 Issued
Array ( [id] => 5919594 [patent_doc_number] => 20060239107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'Memory system and memory device having a serial interface' [patent_app_type] => utility [patent_app_number] => 11/114807 [patent_app_country] => US [patent_app_date] => 2005-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2082 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20060239107.pdf [firstpage_image] =>[orig_patent_app_number] => 11114807 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/114807
Memory system and memory device having a serial interface Apr 25, 2005 Issued
Array ( [id] => 603486 [patent_doc_number] => 07433256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-07 [patent_title] => 'Information carrier, and system for positioning such an information carrier in a reading and/or writing apparatus' [patent_app_type] => utility [patent_app_number] => 11/568243 [patent_app_country] => US [patent_app_date] => 2005-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 7233 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/433/07433256.pdf [firstpage_image] =>[orig_patent_app_number] => 11568243 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/568243
Information carrier, and system for positioning such an information carrier in a reading and/or writing apparatus Apr 20, 2005 Issued
Array ( [id] => 603485 [patent_doc_number] => 07433255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-07 [patent_title] => 'Information carrier, and system for positioning such an information carrier in an apparatus' [patent_app_type] => utility [patent_app_number] => 11/568241 [patent_app_country] => US [patent_app_date] => 2005-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 6172 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/433/07433255.pdf [firstpage_image] =>[orig_patent_app_number] => 11568241 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/568241
Information carrier, and system for positioning such an information carrier in an apparatus Apr 20, 2005 Issued
Array ( [id] => 4838540 [patent_doc_number] => 20080279025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'Electronic Circuit with Memory for Which a Threshold Level is Selected' [patent_app_type] => utility [patent_app_number] => 11/568003 [patent_app_country] => US [patent_app_date] => 2005-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6998 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0279/20080279025.pdf [firstpage_image] =>[orig_patent_app_number] => 11568003 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/568003
Electronic Circuit with Memory for Which a Threshold Level is Selected Apr 20, 2005 Abandoned
Array ( [id] => 6911114 [patent_doc_number] => 20050174872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-11 [patent_title] => 'Line drivers that fits within a specified line pitch' [patent_app_type] => utility [patent_app_number] => 11/024279 [patent_app_country] => US [patent_app_date] => 2005-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 9193 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20050174872.pdf [firstpage_image] =>[orig_patent_app_number] => 11024279 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/024279
Line drivers that fits within a specified line pitch Apr 13, 2005 Issued
Array ( [id] => 902511 [patent_doc_number] => 07339810 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-03-04 [patent_title] => 'Device and method for ensuring current consumption in search engine system' [patent_app_type] => utility [patent_app_number] => 11/089837 [patent_app_country] => US [patent_app_date] => 2005-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 17 [patent_no_of_words] => 4712 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/339/07339810.pdf [firstpage_image] =>[orig_patent_app_number] => 11089837 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/089837
Device and method for ensuring current consumption in search engine system Mar 23, 2005 Issued
Array ( [id] => 426307 [patent_doc_number] => 07272067 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-18 [patent_title] => 'Electrically-programmable integrated circuit antifuses' [patent_app_type] => utility [patent_app_number] => 11/060925 [patent_app_country] => US [patent_app_date] => 2005-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 7587 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/272/07272067.pdf [firstpage_image] =>[orig_patent_app_number] => 11060925 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/060925
Electrically-programmable integrated circuit antifuses Feb 17, 2005 Issued
Array ( [id] => 528165 [patent_doc_number] => 07190629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-13 [patent_title] => 'Circuit and method for reading an antifuse' [patent_app_type] => utility [patent_app_number] => 11/054645 [patent_app_country] => US [patent_app_date] => 2005-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6188 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/190/07190629.pdf [firstpage_image] =>[orig_patent_app_number] => 11054645 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/054645
Circuit and method for reading an antifuse Feb 7, 2005 Issued
Array ( [id] => 5864345 [patent_doc_number] => 20060098475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Static random access memory and pseudo-static noise margin measuring method' [patent_app_type] => utility [patent_app_number] => 11/022791 [patent_app_country] => US [patent_app_date] => 2004-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4519 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20060098475.pdf [firstpage_image] =>[orig_patent_app_number] => 11022791 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/022791
Static random access memory and pseudo-static noise margin measuring method Dec 27, 2004 Issued
Array ( [id] => 631906 [patent_doc_number] => 07133324 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-07 [patent_title] => 'Synchronous dynamic random access memory devices having dual data rate 1 (DDR1) and DDR2 modes of operation and methods of operating same' [patent_app_type] => utility [patent_app_number] => 11/021889 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 33 [patent_no_of_words] => 40936 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/133/07133324.pdf [firstpage_image] =>[orig_patent_app_number] => 11021889 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/021889
Synchronous dynamic random access memory devices having dual data rate 1 (DDR1) and DDR2 modes of operation and methods of operating same Dec 22, 2004 Issued
Array ( [id] => 568916 [patent_doc_number] => 07161845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-09 [patent_title] => 'Static random access memory device having a memory cell with multiple bit-elements' [patent_app_type] => utility [patent_app_number] => 10/905283 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 4968 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/161/07161845.pdf [firstpage_image] =>[orig_patent_app_number] => 10905283 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/905283
Static random access memory device having a memory cell with multiple bit-elements Dec 22, 2004 Issued
Array ( [id] => 7044408 [patent_doc_number] => 20050249003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-10 [patent_title] => 'Semiconductor memory device for reducing cell area' [patent_app_type] => utility [patent_app_number] => 11/017683 [patent_app_country] => US [patent_app_date] => 2004-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3317 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20050249003.pdf [firstpage_image] =>[orig_patent_app_number] => 11017683 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/017683
Semiconductor memory device for reducing cell area Dec 21, 2004 Issued
Array ( [id] => 718901 [patent_doc_number] => 07054199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-30 [patent_title] => 'Multi level flash memory device and program method' [patent_app_type] => utility [patent_app_number] => 11/021181 [patent_app_country] => US [patent_app_date] => 2004-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 3008 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/054/07054199.pdf [firstpage_image] =>[orig_patent_app_number] => 11021181 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/021181
Multi level flash memory device and program method Dec 21, 2004 Issued
Array ( [id] => 426310 [patent_doc_number] => 07272070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-18 [patent_title] => 'Memory access using multiple activated memory cell rows' [patent_app_type] => utility [patent_app_number] => 11/018313 [patent_app_country] => US [patent_app_date] => 2004-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6297 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/272/07272070.pdf [firstpage_image] =>[orig_patent_app_number] => 11018313 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/018313
Memory access using multiple activated memory cell rows Dec 20, 2004 Issued
Array ( [id] => 7038152 [patent_doc_number] => 20050157586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Arrangement comprising a memory device and a program-controlled unit' [patent_app_type] => utility [patent_app_number] => 11/018327 [patent_app_country] => US [patent_app_date] => 2004-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6462 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20050157586.pdf [firstpage_image] =>[orig_patent_app_number] => 11018327 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/018327
Arrangement comprising a memory device and a program-controlled unit Dec 20, 2004 Issued
Array ( [id] => 897851 [patent_doc_number] => 07342841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-11 [patent_title] => 'Method, apparatus, and system for active refresh management' [patent_app_type] => utility [patent_app_number] => 11/019881 [patent_app_country] => US [patent_app_date] => 2004-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3234 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/342/07342841.pdf [firstpage_image] =>[orig_patent_app_number] => 11019881 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/019881
Method, apparatus, and system for active refresh management Dec 20, 2004 Issued
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