Search

Dakota M Talbert

Examiner (ID: 4286)

Most Active Art Unit
2841
Art Unit(s)
2841
Total Applications
46
Issued Applications
8
Pending Applications
36
Abandoned Applications
2

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9753923 [patent_doc_number] => 20140284623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/205964 [patent_app_country] => US [patent_app_date] => 2014-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 16587 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14205964 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/205964
SiC semiconductor device and method of manufacturing the same Mar 11, 2014 Issued
Array ( [id] => 11207965 [patent_doc_number] => 09437596 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'Semiconductor device and method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/206345 [patent_app_country] => US [patent_app_date] => 2014-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 32 [patent_no_of_words] => 9100 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14206345 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/206345
Semiconductor device and method for manufacturing semiconductor device Mar 11, 2014 Issued
Array ( [id] => 10971766 [patent_doc_number] => 20140374801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-25 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/206032 [patent_app_country] => US [patent_app_date] => 2014-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5756 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14206032 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/206032
Semiconductor having a normally-on nitride semiconductor transistor and a normally-off silicon semiconductor transistor provided on different metal substrates Mar 11, 2014 Issued
Array ( [id] => 9753969 [patent_doc_number] => 20140284669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'OPTOELECTRONIC INTEGRATED DEVICE INCLUDING A PHOTODETECTOR AND A MOSFET TRANSISTOR, AND MANUFACTURING PROCESS THEREOF' [patent_app_type] => utility [patent_app_number] => 14/206328 [patent_app_country] => US [patent_app_date] => 2014-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8378 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14206328 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/206328
Optoelectronic integrated device including a photodetector and a MOSFET transistor, and manufacturing process thereof Mar 11, 2014 Issued
Array ( [id] => 10093348 [patent_doc_number] => 09130180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-08 [patent_title] => 'Image sensor with organic photoelectric layer' [patent_app_type] => utility [patent_app_number] => 14/206229 [patent_app_country] => US [patent_app_date] => 2014-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 6285 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14206229 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/206229
Image sensor with organic photoelectric layer Mar 11, 2014 Issued
Array ( [id] => 9753895 [patent_doc_number] => 20140284595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME' [patent_app_type] => utility [patent_app_number] => 14/204365 [patent_app_country] => US [patent_app_date] => 2014-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 18397 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14204365 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/204365
Thin film transistor with multi-layer source/drain electrodes Mar 10, 2014 Issued
Array ( [id] => 9737633 [patent_doc_number] => 20140273351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'METHOD OF ENCAPSULATING A MICRO-DEVICE BY ANODIC BONDING' [patent_app_type] => utility [patent_app_number] => 14/198947 [patent_app_country] => US [patent_app_date] => 2014-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4155 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14198947 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/198947
Method of encapsulating a micro-device by anodic bonding Mar 5, 2014 Issued
Array ( [id] => 9565912 [patent_doc_number] => 20140183626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'DEVICES WITH CAVITY-DEFINED GATES AND METHODS OF MAKING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/198937 [patent_app_country] => US [patent_app_date] => 2014-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 3957 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14198937 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/198937
Devices with cavity-defined gates and methods of making the same Mar 5, 2014 Issued
Array ( [id] => 9762222 [patent_doc_number] => 08846544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-30 [patent_title] => 'Reverse recovery using oxygen-vacancy defects' [patent_app_type] => utility [patent_app_number] => 14/193434 [patent_app_country] => US [patent_app_date] => 2014-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 6120 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14193434 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/193434
Reverse recovery using oxygen-vacancy defects Feb 27, 2014 Issued
Array ( [id] => 10358558 [patent_doc_number] => 20150243563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-27 [patent_title] => 'INTEGRATED CIRCUIT HAVING MULTIPLE THRESHOLD VOLTAGES' [patent_app_type] => utility [patent_app_number] => 14/189085 [patent_app_country] => US [patent_app_date] => 2014-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 14295 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14189085 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/189085
Integrated circuit having multiple threshold voltages Feb 24, 2014 Issued
Array ( [id] => 11227475 [patent_doc_number] => 09455201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-27 [patent_title] => 'Integration method for fabrication of metal gate based multiple threshold voltage devices and circuits' [patent_app_type] => utility [patent_app_number] => 14/188898 [patent_app_country] => US [patent_app_date] => 2014-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 30 [patent_no_of_words] => 14557 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 425 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14188898 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/188898
Integration method for fabrication of metal gate based multiple threshold voltage devices and circuits Feb 24, 2014 Issued
Array ( [id] => 10358880 [patent_doc_number] => 20150243885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-27 [patent_title] => 'CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME' [patent_app_type] => utility [patent_app_number] => 14/189265 [patent_app_country] => US [patent_app_date] => 2014-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8393 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14189265 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/189265
Cross-point memory and methods for fabrication of same Feb 24, 2014 Issued
Array ( [id] => 10358498 [patent_doc_number] => 20150243503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-27 [patent_title] => 'STACKED SIDEWALL PATTERNING' [patent_app_type] => utility [patent_app_number] => 14/188883 [patent_app_country] => US [patent_app_date] => 2014-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5253 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14188883 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/188883
Stacked sidewall patterning Feb 24, 2014 Issued
Array ( [id] => 9534515 [patent_doc_number] => 20140159161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-12 [patent_title] => 'MEASUREMENT OF CMOS DEVICE CHANNEL STRAIN BY X-RAY DIFFRACTION' [patent_app_type] => utility [patent_app_number] => 14/179035 [patent_app_country] => US [patent_app_date] => 2014-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9242 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14179035 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/179035
MEASUREMENT OF CMOS DEVICE CHANNEL STRAIN BY X-RAY DIFFRACTION Feb 11, 2014 Abandoned
Array ( [id] => 10870180 [patent_doc_number] => 08895376 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Thin film transistor, method for manufacturing same, display device, and method for manufacturing same' [patent_app_type] => utility [patent_app_number] => 14/165093 [patent_app_country] => US [patent_app_date] => 2014-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 51 [patent_no_of_words] => 19918 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 362 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14165093 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/165093
Thin film transistor, method for manufacturing same, display device, and method for manufacturing same Jan 26, 2014 Issued
Array ( [id] => 9728537 [patent_doc_number] => 20140264244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'NONVOLATIVE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/162721 [patent_app_country] => US [patent_app_date] => 2014-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 14995 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14162721 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/162721
Nonvolative memory Jan 22, 2014 Issued
Array ( [id] => 9446272 [patent_doc_number] => 20140117440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-01 [patent_title] => 'SEMICONDUCTOR DEVICE WITH IMPURITY REGION WITH INCREASED CONTACT AREA' [patent_app_type] => utility [patent_app_number] => 14/149348 [patent_app_country] => US [patent_app_date] => 2014-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 14695 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14149348 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/149348
SEMICONDUCTOR DEVICE WITH IMPURITY REGION WITH INCREASED CONTACT AREA Jan 6, 2014 Abandoned
Array ( [id] => 9777837 [patent_doc_number] => 08853042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-07 [patent_title] => 'Carbon and nitrogen doping for selected PMOS transistors on an integrated circuit' [patent_app_type] => utility [patent_app_number] => 14/148840 [patent_app_country] => US [patent_app_date] => 2014-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7488 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14148840 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/148840
Carbon and nitrogen doping for selected PMOS transistors on an integrated circuit Jan 6, 2014 Issued
Array ( [id] => 9662970 [patent_doc_number] => 08809954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'Partially depleted (PD) semiconductor-on-insulator (SOI) field effect transistor (FET) structure with a gate-to-body tunnel current region for threshold voltage (Vt) lowering and method of forming the structure' [patent_app_type] => utility [patent_app_number] => 14/146869 [patent_app_country] => US [patent_app_date] => 2014-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 10413 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14146869 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/146869
Partially depleted (PD) semiconductor-on-insulator (SOI) field effect transistor (FET) structure with a gate-to-body tunnel current region for threshold voltage (Vt) lowering and method of forming the structure Jan 2, 2014 Issued
Array ( [id] => 9477488 [patent_doc_number] => 20140134950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'Vertical System Integration' [patent_app_type] => utility [patent_app_number] => 14/143385 [patent_app_country] => US [patent_app_date] => 2013-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 82238 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14143385 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/143385
Vertical System Integration Dec 29, 2013 Abandoned
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