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Dakota M Talbert

Examiner (ID: 4286)

Most Active Art Unit
2841
Art Unit(s)
2841
Total Applications
46
Issued Applications
8
Pending Applications
36
Abandoned Applications
2

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18423957 [patent_doc_number] => 20230178421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => SUBTRACTIVE LINE WITH DAMASCENE TOP VIA [patent_app_type] => utility [patent_app_number] => 17/544136 [patent_app_country] => US [patent_app_date] => 2021-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4132 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17544136 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/544136
SUBTRACTIVE LINE WITH DAMASCENE TOP VIA Dec 6, 2021 Pending
Array ( [id] => 17431689 [patent_doc_number] => 20220059398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => METHOD FOR PREPARING SEMICONDUCTOR DEVICE STRUCTURE WITH AIR GAP [patent_app_type] => utility [patent_app_number] => 17/516696 [patent_app_country] => US [patent_app_date] => 2021-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17516696 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/516696
Method for preparing semiconductor device structure with air gap Nov 1, 2021 Issued
Array ( [id] => 17347274 [patent_doc_number] => 20220013605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/486164 [patent_app_country] => US [patent_app_date] => 2021-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5678 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17486164 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/486164
Display apparatus having self-aligned structures Sep 26, 2021 Issued
Array ( [id] => 18265178 [patent_doc_number] => 20230086420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => SELF ALIGNED QUADRUPLE PATTERNING INTERCONNECTS [patent_app_type] => utility [patent_app_number] => 17/479660 [patent_app_country] => US [patent_app_date] => 2021-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5683 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17479660 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/479660
SELF ALIGNED QUADRUPLE PATTERNING INTERCONNECTS Sep 19, 2021 Pending
Array ( [id] => 17318934 [patent_doc_number] => 20210407984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => FABRICATING METHOD OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/472705 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6573 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17472705 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/472705
Fabricating method of semiconductor device with exposed input/output pad in recess Sep 12, 2021 Issued
Array ( [id] => 18222507 [patent_doc_number] => 20230061501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE HAVING AIR GAP AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/458884 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8704 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17458884 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/458884
SEMICONDUCTOR DEVICE STRUCTURE HAVING AIR GAP AND METHODS OF FORMING THE SAME Aug 26, 2021 Pending
Array ( [id] => 18156203 [patent_doc_number] => 11569196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Chip to chip interconnect in encapsulant of molded semiconductor package [patent_app_type] => utility [patent_app_number] => 17/412787 [patent_app_country] => US [patent_app_date] => 2021-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5127 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17412787 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/412787
Chip to chip interconnect in encapsulant of molded semiconductor package Aug 25, 2021 Issued
Array ( [id] => 17523065 [patent_doc_number] => 20220108914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => Treatment methods for titanium nitride films [patent_app_type] => utility [patent_app_number] => 17/398899 [patent_app_country] => US [patent_app_date] => 2021-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6370 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17398899 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/398899
Treatment methods for titanium nitride films Aug 9, 2021 Pending
Array ( [id] => 17247213 [patent_doc_number] => 20210366958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/392733 [patent_app_country] => US [patent_app_date] => 2021-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9161 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17392733 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/392733
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD Aug 2, 2021 Pending
Array ( [id] => 17993226 [patent_doc_number] => 20220359263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => Devices with Reduced Capacitances [patent_app_type] => utility [patent_app_number] => 17/382873 [patent_app_country] => US [patent_app_date] => 2021-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7035 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17382873 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/382873
Devices with reduced capacitances Jul 21, 2021 Issued
Array ( [id] => 17203486 [patent_doc_number] => 20210343581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME [patent_app_type] => utility [patent_app_number] => 17/373885 [patent_app_country] => US [patent_app_date] => 2021-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5609 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17373885 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/373885
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME Jul 12, 2021 Pending
Array ( [id] => 17347078 [patent_doc_number] => 20220013409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => METHOD FOR MANUFACTURING WIRING SUBSTRATE [patent_app_type] => utility [patent_app_number] => 17/361522 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8241 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17361522 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/361522
Method for manufacturing wiring substrate Jun 28, 2021 Issued
Array ( [id] => 17115570 [patent_doc_number] => 20210296167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => METHODS FOR RELIABLY FORMING MICROELECTRONIC DEVICES WITH CONDUCTIVE CONTACTS TO SILICIDE REGIONS, AND RELATED SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/340410 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9686 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340410 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/340410
METHODS FOR RELIABLY FORMING MICROELECTRONIC DEVICES WITH CONDUCTIVE CONTACTS TO SILICIDE REGIONS, AND RELATED SYSTEMS Jun 6, 2021 Pending
Array ( [id] => 17085776 [patent_doc_number] => 20210280783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => STEP HEIGHT MITIGATION IN RESISTIVE RANDOM ACCESS MEMORY STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/329247 [patent_app_country] => US [patent_app_date] => 2021-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7910 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17329247 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/329247
Step height mitigation in resistive random access memory structures May 24, 2021 Issued
Array ( [id] => 17053934 [patent_doc_number] => 20210263368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/317890 [patent_app_country] => US [patent_app_date] => 2021-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17317890 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/317890
DISPLAY DEVICE May 11, 2021 Abandoned
Array ( [id] => 17941696 [patent_doc_number] => 11476155 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Patterning method [patent_app_type] => utility [patent_app_number] => 17/237699 [patent_app_country] => US [patent_app_date] => 2021-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 12000 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17237699 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/237699
Patterning method Apr 21, 2021 Issued
Array ( [id] => 17158982 [patent_doc_number] => 20210320033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/225450 [patent_app_country] => US [patent_app_date] => 2021-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4805 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17225450 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/225450
Method of manufacturing semiconductor device Apr 7, 2021 Issued
Array ( [id] => 17145204 [patent_doc_number] => 20210313217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => FORMING VIAS IN A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/223876 [patent_app_country] => US [patent_app_date] => 2021-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11413 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17223876 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/223876
FORMING VIAS IN A SEMICONDUCTOR DEVICE Apr 5, 2021 Pending
Array ( [id] => 17893270 [patent_doc_number] => 11456252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-27 [patent_title] => Semiconductor device having symmetric conductive interconnection patterns [patent_app_type] => utility [patent_app_number] => 17/189839 [patent_app_country] => US [patent_app_date] => 2021-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4894 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17189839 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/189839
Semiconductor device having symmetric conductive interconnection patterns Mar 1, 2021 Issued
Array ( [id] => 16904852 [patent_doc_number] => 20210183768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => INTEGRATED CIRCUITS INCLUDING VIA ARRAY AND METHODS OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/188414 [patent_app_country] => US [patent_app_date] => 2021-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12307 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17188414 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/188414
INTEGRATED CIRCUITS INCLUDING VIA ARRAY AND METHODS OF MANUFACTURING THE SAME Feb 28, 2021 Pending
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