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Dakota M Talbert

Examiner (ID: 4286)

Most Active Art Unit
2841
Art Unit(s)
2841
Total Applications
46
Issued Applications
8
Pending Applications
36
Abandoned Applications
2

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16888997 [patent_doc_number] => 20210175194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => BOND PAD WITH MICRO-PROTRUSIONS FOR DIRECT METALLIC BONDING [patent_app_type] => utility [patent_app_number] => 17/174827 [patent_app_country] => US [patent_app_date] => 2021-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17174827 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/174827
BOND PAD WITH MICRO-PROTRUSIONS FOR DIRECT METALLIC BONDING Feb 11, 2021 Pending
Array ( [id] => 18704687 [patent_doc_number] => 11791204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Semiconductor device with connecting structure having a doped layer and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/171210 [patent_app_country] => US [patent_app_date] => 2021-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 10864 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17171210 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/171210
Semiconductor device with connecting structure having a doped layer and method for forming the same Feb 8, 2021 Issued
Array ( [id] => 18073747 [patent_doc_number] => 11532587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => Method for manufacturing semiconductor package with connection structures including via groups [patent_app_type] => utility [patent_app_number] => 17/170268 [patent_app_country] => US [patent_app_date] => 2021-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 52 [patent_no_of_words] => 7809 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17170268 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/170268
Method for manufacturing semiconductor package with connection structures including via groups Feb 7, 2021 Issued
Array ( [id] => 17010991 [patent_doc_number] => 20210242152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => SELECTIVE ALTERATION OF INTERCONNECT PADS FOR DIRECT BONDING [patent_app_type] => utility [patent_app_number] => 17/168034 [patent_app_country] => US [patent_app_date] => 2021-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17168034 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/168034
SELECTIVE ALTERATION OF INTERCONNECT PADS FOR DIRECT BONDING Feb 3, 2021 Pending
Array ( [id] => 17780184 [patent_doc_number] => 20220246534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => LOW-RESISTANCE COPPER INTERCONNECTS [patent_app_type] => utility [patent_app_number] => 17/248594 [patent_app_country] => US [patent_app_date] => 2021-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22261 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17248594 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/248594
LOW-RESISTANCE COPPER INTERCONNECTS Jan 28, 2021 Pending
Array ( [id] => 16781752 [patent_doc_number] => 20210118831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => SEMICONDUCTOR DEVICE BONDING AREA INCLUDING FUSED SOLDER FILM AND MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/137657 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4441 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/137657
Semiconductor device bonding area including fused solder film and manufacturing method Dec 29, 2020 Issued
Array ( [id] => 18031961 [patent_doc_number] => 11515159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Forming contact holes using litho-etch-litho-etch approach [patent_app_type] => utility [patent_app_number] => 17/137320 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4221 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137320 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/137320
Forming contact holes using litho-etch-litho-etch approach Dec 28, 2020 Issued
Array ( [id] => 17676651 [patent_doc_number] => 20220189818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => ULTRALOW-K DIELECTRIC-GAP WRAPPED CONTACTS AND METHOD [patent_app_type] => utility [patent_app_number] => 17/118697 [patent_app_country] => US [patent_app_date] => 2020-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8874 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17118697 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/118697
Ultralow-K dielectric-gap wrapped contacts and method Dec 10, 2020 Issued
Array ( [id] => 16765728 [patent_doc_number] => 20210111310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => LIGHT EMITTING CHIP AND ASSOCIATED PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/106990 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5552 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17106990 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/106990
LIGHT EMITTING CHIP AND ASSOCIATED PACKAGE STRUCTURE Nov 29, 2020 Abandoned
Array ( [id] => 17262684 [patent_doc_number] => 20210375669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => SURFACE UNIFORMITY CONTROL IN PIXEL STRUCTURES OF IMAGE SENSORS [patent_app_type] => utility [patent_app_number] => 17/102623 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7712 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17102623 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/102623
SURFACE UNIFORMITY CONTROL IN PIXEL STRUCTURES OF IMAGE SENSORS Nov 23, 2020 Pending
Array ( [id] => 16850627 [patent_doc_number] => 20210151372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/951584 [patent_app_country] => US [patent_app_date] => 2020-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8896 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16951584 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/951584
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Nov 17, 2020 Pending
Array ( [id] => 17615373 [patent_doc_number] => 20220157653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/097409 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6989 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17097409 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/097409
Method for forming semiconductor device structure with source/drain contact Nov 12, 2020 Issued
Array ( [id] => 19093914 [patent_doc_number] => 11955379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Metal adhesion layer to promote metal plug adhesion [patent_app_type] => utility [patent_app_number] => 17/021776 [patent_app_country] => US [patent_app_date] => 2020-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6957 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17021776 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/021776
Metal adhesion layer to promote metal plug adhesion Sep 14, 2020 Issued
Array ( [id] => 17115678 [patent_doc_number] => 20210296275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THEREOF [patent_app_type] => utility [patent_app_number] => 17/017464 [patent_app_country] => US [patent_app_date] => 2020-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17017464 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/017464
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THEREOF Sep 9, 2020 Abandoned
Array ( [id] => 19016349 [patent_doc_number] => 11923291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Via connection to wiring in a semiconductor device [patent_app_type] => utility [patent_app_number] => 17/007626 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 7717 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17007626 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/007626
Via connection to wiring in a semiconductor device Aug 30, 2020 Issued
Array ( [id] => 17787721 [patent_doc_number] => 11410855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Method of producing electroconductive substrate, electronic device and display device [patent_app_type] => utility [patent_app_number] => 16/997092 [patent_app_country] => US [patent_app_date] => 2020-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 31 [patent_no_of_words] => 11159 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16997092 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/997092
Method of producing electroconductive substrate, electronic device and display device Aug 18, 2020 Issued
Array ( [id] => 16920414 [patent_doc_number] => 20210193506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => BILAYER SEAL MATERIAL FOR AIR GAPS IN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/937237 [patent_app_country] => US [patent_app_date] => 2020-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11039 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16937237 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/937237
Bilayer seal material for air gaps in semiconductor devices Jul 22, 2020 Issued
Array ( [id] => 16601528 [patent_doc_number] => 20210028059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => Method for Forming a Buried Metal Line in a Semiconductor Substrate [patent_app_type] => utility [patent_app_number] => 16/934200 [patent_app_country] => US [patent_app_date] => 2020-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5389 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16934200 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/934200
Method for Forming a Buried Metal Line in a Semiconductor Substrate Jul 20, 2020 Abandoned
Array ( [id] => 18263102 [patent_doc_number] => 11610811 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Semiconductor device with covering liners and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 16/902692 [patent_app_country] => US [patent_app_date] => 2020-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 9328 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16902692 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/902692
Semiconductor device with covering liners and method for fabricating the same Jun 15, 2020 Issued
Array ( [id] => 17277942 [patent_doc_number] => 20210384140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => SEMICONDUCTOR DEVICE WITH ADJUSTMENT LAYERS AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/895620 [patent_app_country] => US [patent_app_date] => 2020-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16895620 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/895620
SEMICONDUCTOR DEVICE WITH ADJUSTMENT LAYERS AND METHOD FOR FABRICATING THE SAME Jun 7, 2020 Abandoned
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