Dakota M Talbert

Array ( [id] => 5268510 [patent_doc_number] => 20090072285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'CMOS IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/211124 [patent_app_country] => US [patent_app_date] => 2008-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1701 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20090072285.pdf [firstpage_image] =>[orig_patent_app_number] => 12211124 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8629823 [patent_doc_number] => 08361895 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-29 [patent_title] => 'Ultra-shallow junctions using atomic-layer doping' [patent_app_type] => utility [patent_app_number] => 12/211464 [patent_app_country] => US [patent_app_date] => 2008-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5532 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12211464 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6570374 [patent_doc_number] => 20100320508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'HORIZONTALLY DEPLETED METAL SEMICONDUCTOR FIELD EFFECT TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 12/677066 [patent_app_country] => US [patent_app_date] => 2008-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 6497 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0320/20100320508.pdf [firstpage_image] =>[orig_patent_app_number] => 12677066 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8283340 [patent_doc_number] => 08217441 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-10 [patent_title] => 'Semiconductor constructions including gate arrays formed on partial SOI substrate' [patent_app_type] => utility [patent_app_number] => 12/186726 [patent_app_country] => US [patent_app_date] => 2008-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 47 [patent_no_of_words] => 7269 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 340 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12186726 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9427506 [patent_doc_number] => 08703580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-22 [patent_title] => 'Silicon on insulator (SOI) wafer and process for producing same' [patent_app_type] => utility [patent_app_number] => 12/163764 [patent_app_country] => US [patent_app_date] => 2008-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4515 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12163764 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8435469 [patent_doc_number] => 08283238 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-09 [patent_title] => 'Layer transfer process for semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/213734 [patent_app_country] => US [patent_app_date] => 2008-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 54 [patent_no_of_words] => 22064 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12213734 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4949446 [patent_doc_number] => 20080305572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-11 [patent_title] => 'METHOD OF FABRICATING IMAGE DEVICE HAVING CAPACITOR AND IMAGE DEVICE FABRICATED THEREBY' [patent_app_type] => utility [patent_app_number] => 12/132542 [patent_app_country] => US [patent_app_date] => 2008-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6935 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0305/20080305572.pdf [firstpage_image] =>[orig_patent_app_number] => 12132542 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8807712 [patent_doc_number] => 08445364 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-21 [patent_title] => 'Methods of treating semiconducting materials including melting and cooling' [patent_app_type] => utility [patent_app_number] => 12/156499 [patent_app_country] => US [patent_app_date] => 2008-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5806 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12156499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 42567 [patent_doc_number] => 07781273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure' [patent_app_type] => utility [patent_app_number] => 12/127033 [patent_app_country] => US [patent_app_date] => 2008-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 6432 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/781/07781273.pdf [firstpage_image] =>[orig_patent_app_number] => 12127033 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6469991 [patent_doc_number] => 20100207120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-19 [patent_title] => 'PRODUCTION METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/676945 [patent_app_country] => US [patent_app_date] => 2008-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13677 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20100207120.pdf [firstpage_image] =>[orig_patent_app_number] => 12676945 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4715069 [patent_doc_number] => 20080237591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Vertical system integration' [patent_app_type] => utility [patent_app_number] => 12/118582 [patent_app_country] => US [patent_app_date] => 2008-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 82243 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20080237591.pdf [firstpage_image] =>[orig_patent_app_number] => 12118582 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4955056 [patent_doc_number] => 20080188080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'MANDREL/TRIM ALIGNMENT IN SIT PROCESSING' [patent_app_type] => utility [patent_app_number] => 12/062618 [patent_app_country] => US [patent_app_date] => 2008-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7529 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20080188080.pdf [firstpage_image] =>[orig_patent_app_number] => 12062618 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4816994 [patent_doc_number] => 20080224253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/046033 [patent_app_country] => US [patent_app_date] => 2008-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11845 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20080224253.pdf [firstpage_image] =>[orig_patent_app_number] => 12046033 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4500055 [patent_doc_number] => 07919377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-05 [patent_title] => 'Contactless flash memory array' [patent_app_type] => utility [patent_app_number] => 12/070928 [patent_app_country] => US [patent_app_date] => 2008-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 31 [patent_no_of_words] => 4591 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/919/07919377.pdf [firstpage_image] =>[orig_patent_app_number] => 12070928 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 159139 [patent_doc_number] => 07674645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-09 [patent_title] => 'Diode energy converter for chemical kinetic electron energy transfer' [patent_app_type] => utility [patent_app_number] => 12/029576 [patent_app_country] => US [patent_app_date] => 2008-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5759 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/674/07674645.pdf [firstpage_image] =>[orig_patent_app_number] => 12029576 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4624164 [patent_doc_number] => 08003460 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Method of forming a semiconductor structure comprising a formation of at least one sidewall spacer structure' [patent_app_type] => utility [patent_app_number] => 12/028895 [patent_app_country] => US [patent_app_date] => 2008-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10275 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/003/08003460.pdf [firstpage_image] =>[orig_patent_app_number] => 12028895 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4843242 [patent_doc_number] => 20080179650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'SEMICONDUCTOR DEVICE, FABRICATION METHOD OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/022363 [patent_app_country] => US [patent_app_date] => 2008-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7411 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20080179650.pdf [firstpage_image] =>[orig_patent_app_number] => 12022363 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5327842 [patent_doc_number] => 20090108319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'DRAM STACK CAPACITOR AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/017164 [patent_app_country] => US [patent_app_date] => 2008-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1395 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20090108319.pdf [firstpage_image] =>[orig_patent_app_number] => 12017164 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5352997 [patent_doc_number] => 20090184341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'Elimination of STI recess and facet growth in embedded silicon-germanium (eSiGe) module\n' [patent_app_type] => utility [patent_app_number] => 12/009204 [patent_app_country] => US [patent_app_date] => 2008-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3079 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20090184341.pdf [firstpage_image] =>[orig_patent_app_number] => 12009204 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5349494 [patent_doc_number] => 20090004855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'METHOD FOR FABRICATING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/965966 [patent_app_country] => US [patent_app_date] => 2007-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6489 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20090004855.pdf [firstpage_image] =>[orig_patent_app_number] => 11965966 [rel_patent_id] =>[rel_patent_doc_number] =>)