Dakota M Talbert
Examiner (ID: 4286)
Most Active Art Unit | 2841 |
Art Unit(s) | 2841 |
Total Applications | 46 |
Issued Applications | 8 |
Pending Applications | 36 |
Abandoned Applications | 2 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 5349436
[patent_doc_number] => 20090004797
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-01-01
[patent_title] => 'METHOD FOR FABRICATING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/965706
[patent_app_country] => US
[patent_app_date] => 2007-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3071
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0004/20090004797.pdf
[firstpage_image] =>[orig_patent_app_number] => 11965706
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/965706 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE | Dec 26, 2007 | Abandoned |
Array
(
[id] => 4833436
[patent_doc_number] => 20080131983
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-05
[patent_title] => 'Method for forming post passivation Au layer with clean surface'
[patent_app_type] => utility
[patent_app_number] => 11/949785
[patent_app_country] => US
[patent_app_date] => 2007-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 54
[patent_figures_cnt] => 54
[patent_no_of_words] => 23894
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0131/20080131983.pdf
[firstpage_image] =>[orig_patent_app_number] => 11949785
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/949785 | Method for forming post passivation Au layer with clean surface | Dec 3, 2007 | Issued |
Array
(
[id] => 5564216
[patent_doc_number] => 20090137069
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-05-28
[patent_title] => 'Chip packaging process including simpification and mergence of burn-in test and high temperature test'
[patent_app_type] => utility
[patent_app_number] => 11/987235
[patent_app_country] => US
[patent_app_date] => 2007-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 3070
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0137/20090137069.pdf
[firstpage_image] =>[orig_patent_app_number] => 11987235
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/987235 | Chip packaging process including simpification and mergence of burn-in test and high temperature test | Nov 27, 2007 | Abandoned |
Array
(
[id] => 4785645
[patent_doc_number] => 20080138974
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-12
[patent_title] => 'Method of sputtering a nickel silicon alloy, especially useful for forming a solder bump barrier'
[patent_app_type] => utility
[patent_app_number] => 11/945856
[patent_app_country] => US
[patent_app_date] => 2007-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4988
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0138/20080138974.pdf
[firstpage_image] =>[orig_patent_app_number] => 11945856
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/945856 | Method of sputtering a nickel silicon alloy, especially useful for forming a solder bump barrier | Nov 26, 2007 | Abandoned |
Array
(
[id] => 4949478
[patent_doc_number] => 20080305604
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-12-11
[patent_title] => 'DEEP TRENCH AND FABRICATING METHOD THEREOF, TRENCH CAPACITOR AND FABRICATING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 11/943586
[patent_app_country] => US
[patent_app_date] => 2007-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4464
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0305/20080305604.pdf
[firstpage_image] =>[orig_patent_app_number] => 11943586
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/943586 | DEEP TRENCH AND FABRICATING METHOD THEREOF, TRENCH CAPACITOR AND FABRICATING METHOD THEREOF | Nov 20, 2007 | Abandoned |
Array
(
[id] => 4752663
[patent_doc_number] => 20080160738
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'Method for fabricating semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/983075
[patent_app_country] => US
[patent_app_date] => 2007-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2243
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0160/20080160738.pdf
[firstpage_image] =>[orig_patent_app_number] => 11983075
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/983075 | Method involving trimming a hard mask in the peripheral region of a semiconductor device | Nov 5, 2007 | Issued |
Array
(
[id] => 4807831
[patent_doc_number] => 20080171409
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-17
[patent_title] => 'METHOD FOR FABRICATING BOTTOM-GATE LOW-TEMPERATURE POLYSILICON THIN FILM TRANSISTOR'
[patent_app_type] => utility
[patent_app_number] => 11/935626
[patent_app_country] => US
[patent_app_date] => 2007-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 3476
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0171/20080171409.pdf
[firstpage_image] =>[orig_patent_app_number] => 11935626
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/935626 | METHOD FOR FABRICATING BOTTOM-GATE LOW-TEMPERATURE POLYSILICON THIN FILM TRANSISTOR | Nov 5, 2007 | Abandoned |
Array
(
[id] => 4752666
[patent_doc_number] => 20080160741
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/933925
[patent_app_country] => US
[patent_app_date] => 2007-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2008
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0160/20080160741.pdf
[firstpage_image] =>[orig_patent_app_number] => 11933925
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/933925 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | Oct 31, 2007 | Abandoned |
Array
(
[id] => 4820856
[patent_doc_number] => 20080122111
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-29
[patent_title] => 'SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 11/933755
[patent_app_country] => US
[patent_app_date] => 2007-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1300
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0122/20080122111.pdf
[firstpage_image] =>[orig_patent_app_number] => 11933755
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/933755 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF | Oct 31, 2007 | Abandoned |
Array
(
[id] => 4698369
[patent_doc_number] => 20080220553
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-11
[patent_title] => 'Method of producing liquid crystal display device including forming an align mark in an insulating mother substrate'
[patent_app_type] => utility
[patent_app_number] => 11/931206
[patent_app_country] => US
[patent_app_date] => 2007-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4904
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0220/20080220553.pdf
[firstpage_image] =>[orig_patent_app_number] => 11931206
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/931206 | Method of producing liquid crystal display device including forming an align mark in an insulating mother substrate | Oct 30, 2007 | Abandoned |
Array
(
[id] => 4752642
[patent_doc_number] => 20080160717
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'Method of Forming Trench in Semiconductor Device'
[patent_app_type] => utility
[patent_app_number] => 11/929966
[patent_app_country] => US
[patent_app_date] => 2007-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2549
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0160/20080160717.pdf
[firstpage_image] =>[orig_patent_app_number] => 11929966
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/929966 | Method of Forming Trench in Semiconductor Device | Oct 29, 2007 | Abandoned |
Array
(
[id] => 5330794
[patent_doc_number] => 20090111271
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-30
[patent_title] => 'ISOTROPIC SILICON ETCH USING ANISOTROPIC ETCHANTS'
[patent_app_type] => utility
[patent_app_number] => 11/925336
[patent_app_country] => US
[patent_app_date] => 2007-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 1123
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0111/20090111271.pdf
[firstpage_image] =>[orig_patent_app_number] => 11925336
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/925336 | ISOTROPIC SILICON ETCH USING ANISOTROPIC ETCHANTS | Oct 25, 2007 | Abandoned |
Array
(
[id] => 5582711
[patent_doc_number] => 20090101913
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-23
[patent_title] => 'APPARATUS AND METHOD FOR REDUCING PHOTO LEAKAGE CURRENT FOR TFT LCD'
[patent_app_type] => utility
[patent_app_number] => 11/873674
[patent_app_country] => US
[patent_app_date] => 2007-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 5831
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0101/20090101913.pdf
[firstpage_image] =>[orig_patent_app_number] => 11873674
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/873674 | Apparatus and method for reducing photo leakage current for TFT LCD | Oct 16, 2007 | Issued |
Array
(
[id] => 5508651
[patent_doc_number] => 20090081858
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-03-26
[patent_title] => 'Sputtering-Less Ultra-Low Energy Ion Implantation'
[patent_app_type] => utility
[patent_app_number] => 11/861665
[patent_app_country] => US
[patent_app_date] => 2007-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6592
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0081/20090081858.pdf
[firstpage_image] =>[orig_patent_app_number] => 11861665
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/861665 | Sputtering-less ultra-low energy ion implantation | Sep 25, 2007 | Issued |
Array
(
[id] => 8802306
[patent_doc_number] => 08440580
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-05-14
[patent_title] => 'Method of fabricating silicon nitride gap-filling layer'
[patent_app_type] => utility
[patent_app_number] => 11/853475
[patent_app_country] => US
[patent_app_date] => 2007-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4391
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11853475
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/853475 | Method of fabricating silicon nitride gap-filling layer | Sep 10, 2007 | Issued |
Array
(
[id] => 4704662
[patent_doc_number] => 20080064186
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-13
[patent_title] => 'Manufacturing method of semiconductor element'
[patent_app_type] => utility
[patent_app_number] => 11/898146
[patent_app_country] => US
[patent_app_date] => 2007-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5417
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0064/20080064186.pdf
[firstpage_image] =>[orig_patent_app_number] => 11898146
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/898146 | Manufacturing method of semiconductor element | Sep 9, 2007 | Abandoned |
Array
(
[id] => 5449784
[patent_doc_number] => 20090065820
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-03-12
[patent_title] => 'Method and structure for simultaneously fabricating selective film and spacer'
[patent_app_type] => utility
[patent_app_number] => 11/851373
[patent_app_country] => US
[patent_app_date] => 2007-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 5861
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0065/20090065820.pdf
[firstpage_image] =>[orig_patent_app_number] => 11851373
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/851373 | Method and structure for simultaneously fabricating selective film and spacer | Sep 5, 2007 | Abandoned |
Array
(
[id] => 4444606
[patent_doc_number] => 07863146
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-01-04
[patent_title] => 'Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance'
[patent_app_type] => utility
[patent_app_number] => 11/851325
[patent_app_country] => US
[patent_app_date] => 2007-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 25
[patent_no_of_words] => 12582
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 290
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/863/07863146.pdf
[firstpage_image] =>[orig_patent_app_number] => 11851325
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/851325 | Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance | Sep 5, 2007 | Issued |
Array
(
[id] => 4772024
[patent_doc_number] => 20080057682
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-06
[patent_title] => 'Manufacturing method of an integrated circuit formed on a semiconductor substrate'
[patent_app_type] => utility
[patent_app_number] => 11/899275
[patent_app_country] => US
[patent_app_date] => 2007-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7517
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0057/20080057682.pdf
[firstpage_image] =>[orig_patent_app_number] => 11899275
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/899275 | Manufacturing method of an integrated circuit formed on a semiconductor substrate | Sep 3, 2007 | Abandoned |
Array
(
[id] => 6547883
[patent_doc_number] => 20100127233
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-05-27
[patent_title] => 'METHOD FOR CONTROLLED FORMATION OF THE RESISTIVE SWITCHING MATERIAL IN A RESISTIVE SWITCHING DEVICE AND DEVICE OBTAINED THEREOF'
[patent_app_type] => utility
[patent_app_number] => 12/439414
[patent_app_country] => US
[patent_app_date] => 2007-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 33
[patent_no_of_words] => 12104
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0127/20100127233.pdf
[firstpage_image] =>[orig_patent_app_number] => 12439414
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/439414 | Method for controlled formation of the resistive switching material in a resistive switching device and device obtained thereof | Aug 30, 2007 | Issued |