Search

Dakota M Talbert

Examiner (ID: 4286)

Most Active Art Unit
2841
Art Unit(s)
2841
Total Applications
46
Issued Applications
8
Pending Applications
36
Abandoned Applications
2

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5361114 [patent_doc_number] => 20090035908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'PROCESS FOR FABRICATING A NANOWIRE-BASED VERTICAL TRANSISTOR STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/278173 [patent_app_country] => US [patent_app_date] => 2007-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3146 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20090035908.pdf [firstpage_image] =>[orig_patent_app_number] => 12278173 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/278173
Process for fabricating a nanowire-based vertical transistor structure Feb 4, 2007 Issued
Array ( [id] => 5085492 [patent_doc_number] => 20070275543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-29 [patent_title] => 'Manufacturing method of a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/700926 [patent_app_country] => US [patent_app_date] => 2007-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8650 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20070275543.pdf [firstpage_image] =>[orig_patent_app_number] => 11700926 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/700926
Manufacturing method of a semiconductor device Jan 31, 2007 Abandoned
Array ( [id] => 5036625 [patent_doc_number] => 20070101164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'INFORMATION STORAGE MEDIUM, INFORMATION REPRODUCING APPARATUS, AND INFORMATION REPRODUCING METHOD' [patent_app_type] => utility [patent_app_number] => 11/564716 [patent_app_country] => US [patent_app_date] => 2006-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 117 [patent_figures_cnt] => 117 [patent_no_of_words] => 173015 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20070101164.pdf [firstpage_image] =>[orig_patent_app_number] => 11564716 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/564716
INFORMATION STORAGE MEDIUM, INFORMATION REPRODUCING APPARATUS, AND INFORMATION REPRODUCING METHOD Nov 28, 2006 Abandoned
Array ( [id] => 345049 [patent_doc_number] => 07498236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-03 [patent_title] => 'Silicon wafer thinning end point method' [patent_app_type] => utility [patent_app_number] => 11/563715 [patent_app_country] => US [patent_app_date] => 2006-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1833 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/498/07498236.pdf [firstpage_image] =>[orig_patent_app_number] => 11563715 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/563715
Silicon wafer thinning end point method Nov 27, 2006 Issued
Array ( [id] => 5222938 [patent_doc_number] => 20070252204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'SOI TRANSISTOR HAVING AN EMBEDDED STRAIN LAYER AND A REDUCED FLOATING BODY EFFECT AND A METHOD FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/563986 [patent_app_country] => US [patent_app_date] => 2006-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8188 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0252/20070252204.pdf [firstpage_image] =>[orig_patent_app_number] => 11563986 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/563986
SOI transistor having an embedded strain layer and a reduced floating body effect and a method for forming the same Nov 27, 2006 Issued
Array ( [id] => 4685629 [patent_doc_number] => 20080029810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING BURIED GATES AND RELATED SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 11/563365 [patent_app_country] => US [patent_app_date] => 2006-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7315 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20080029810.pdf [firstpage_image] =>[orig_patent_app_number] => 11563365 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/563365
METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING BURIED GATES AND RELATED SEMICONDUCTOR DEVICES Nov 26, 2006 Abandoned
Array ( [id] => 4899408 [patent_doc_number] => 20080119022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-22 [patent_title] => 'METHOD OF MAKING EEPROM TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 11/562776 [patent_app_country] => US [patent_app_date] => 2006-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2713 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20080119022.pdf [firstpage_image] =>[orig_patent_app_number] => 11562776 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/562776
METHOD OF MAKING EEPROM TRANSISTORS Nov 21, 2006 Abandoned
Array ( [id] => 5101369 [patent_doc_number] => 20070184631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'METHOD OF MANUFACTURING BONDED WAFER' [patent_app_type] => utility [patent_app_number] => 11/562635 [patent_app_country] => US [patent_app_date] => 2006-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3144 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20070184631.pdf [firstpage_image] =>[orig_patent_app_number] => 11562635 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/562635
METHOD OF MANUFACTURING BONDED WAFER Nov 21, 2006 Abandoned
Array ( [id] => 7692000 [patent_doc_number] => 20070232033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'METHOD FOR FORMING ULTRA-SHALLOW HIGH QUALITY JUNCTIONS BY A COMBINATION OF SOLID PHASE EPITAXY AND LASER ANNEALING' [patent_app_type] => utility [patent_app_number] => 11/562445 [patent_app_country] => US [patent_app_date] => 2006-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5328 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20070232033.pdf [firstpage_image] =>[orig_patent_app_number] => 11562445 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/562445
METHOD FOR FORMING ULTRA-SHALLOW HIGH QUALITY JUNCTIONS BY A COMBINATION OF SOLID PHASE EPITAXY AND LASER ANNEALING Nov 21, 2006 Abandoned
Array ( [id] => 5250549 [patent_doc_number] => 20070132005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'Electrically Erasable and Programmable Read Only Memories Including Variable Width Overlap Regions and Methods of Fabricating the Same' [patent_app_type] => utility [patent_app_number] => 11/562223 [patent_app_country] => US [patent_app_date] => 2006-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7340 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20070132005.pdf [firstpage_image] =>[orig_patent_app_number] => 11562223 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/562223
Electrically Erasable and Programmable Read Only Memories Including Variable Width Overlap Regions and Methods of Fabricating the Same Nov 20, 2006 Abandoned
Array ( [id] => 5046117 [patent_doc_number] => 20070264790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-15 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/557885 [patent_app_country] => US [patent_app_date] => 2006-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1224 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0264/20070264790.pdf [firstpage_image] =>[orig_patent_app_number] => 11557885 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/557885
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Nov 7, 2006 Abandoned
Array ( [id] => 4820688 [patent_doc_number] => 20080121985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'STRUCTURE AND METHOD TO IMPROVE SHORT CHANNEL EFFECTS IN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 11/557145 [patent_app_country] => US [patent_app_date] => 2006-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7057 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20080121985.pdf [firstpage_image] =>[orig_patent_app_number] => 11557145 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/557145
STRUCTURE AND METHOD TO IMPROVE SHORT CHANNEL EFFECTS IN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS Nov 6, 2006 Abandoned
Array ( [id] => 5157450 [patent_doc_number] => 20070170494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'Nonvolatile memory device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/584965 [patent_app_country] => US [patent_app_date] => 2006-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6491 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20070170494.pdf [firstpage_image] =>[orig_patent_app_number] => 11584965 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/584965
Nonvolatile memory device and method for fabricating the same Oct 22, 2006 Abandoned
Array ( [id] => 4915757 [patent_doc_number] => 20080096357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'METHOD FOR MANUFACTURING A MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/551535 [patent_app_country] => US [patent_app_date] => 2006-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3996 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20080096357.pdf [firstpage_image] =>[orig_patent_app_number] => 11551535 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/551535
METHOD FOR MANUFACTURING A MEMORY DEVICE Oct 19, 2006 Abandoned
Array ( [id] => 5040714 [patent_doc_number] => 20070092996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'METHOD OF MAKING SEMICONDUCTOR PACKAGE WITH REDUCED MOISTURE SENSITIVITY' [patent_app_type] => utility [patent_app_number] => 11/551615 [patent_app_country] => US [patent_app_date] => 2006-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2722 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20070092996.pdf [firstpage_image] =>[orig_patent_app_number] => 11551615 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/551615
METHOD OF MAKING SEMICONDUCTOR PACKAGE WITH REDUCED MOISTURE SENSITIVITY Oct 19, 2006 Abandoned
Array ( [id] => 4745749 [patent_doc_number] => 20080090351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'FABRICATING NON-VOLATILE MEMORY WITH DUAL VOLTAGE SELECT GATE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 11/550386 [patent_app_country] => US [patent_app_date] => 2006-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 19451 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20080090351.pdf [firstpage_image] =>[orig_patent_app_number] => 11550386 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/550386
Fabricating non-volatile memory with dual voltage select gate structure Oct 16, 2006 Issued
Array ( [id] => 4743364 [patent_doc_number] => 20080087965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'STRUCTURE AND METHOD OF FORMING TRANSISTOR DENSITY BASED STRESS LAYERS IN CMOS DEVICES' [patent_app_type] => utility [patent_app_number] => 11/548296 [patent_app_country] => US [patent_app_date] => 2006-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2340 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20080087965.pdf [firstpage_image] =>[orig_patent_app_number] => 11548296 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/548296
STRUCTURE AND METHOD OF FORMING TRANSISTOR DENSITY BASED STRESS LAYERS IN CMOS DEVICES Oct 10, 2006 Abandoned
Array ( [id] => 5193956 [patent_doc_number] => 20070082440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/544616 [patent_app_country] => US [patent_app_date] => 2006-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 6574 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20070082440.pdf [firstpage_image] =>[orig_patent_app_number] => 11544616 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/544616
Method for forming a gate within a trench including the use of a protective film Oct 9, 2006 Issued
Array ( [id] => 4691156 [patent_doc_number] => 20080083926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'Printing device structures using nanoparticles' [patent_app_type] => utility [patent_app_number] => 11/546026 [patent_app_country] => US [patent_app_date] => 2006-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3910 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20080083926.pdf [firstpage_image] =>[orig_patent_app_number] => 11546026 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/546026
Printing device structures using nanoparticles Oct 9, 2006 Abandoned
Array ( [id] => 4982976 [patent_doc_number] => 20070087534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'ELECTRO-OPTICAL DEVICE, METHOD OF MANUFACTURING THE SAME, ELECTRONIC APPARATUS, AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/539466 [patent_app_country] => US [patent_app_date] => 2006-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11287 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20070087534.pdf [firstpage_image] =>[orig_patent_app_number] => 11539466 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/539466
Electro-optical device, method of manufacturing the same, electronic apparatus, and semiconductor device Oct 5, 2006 Issued
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