Dakota M Talbert

Array ( [id] => 5222932 [patent_doc_number] => 20070252198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'Semiconductor device having a fin channel transistor' [patent_app_type] => utility [patent_app_number] => 11/529355 [patent_app_country] => US [patent_app_date] => 2006-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4223 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0252/20070252198.pdf [firstpage_image] =>[orig_patent_app_number] => 11529355 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5105611 [patent_doc_number] => 20070064486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-22 [patent_title] => 'Display device and fabricating method thereof' [patent_app_type] => utility [patent_app_number] => 11/525273 [patent_app_country] => US [patent_app_date] => 2006-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5185 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20070064486.pdf [firstpage_image] =>[orig_patent_app_number] => 11525273 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5188609 [patent_doc_number] => 20070166917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Non-volatile memory device and fabricating method therefor' [patent_app_type] => utility [patent_app_number] => 11/519655 [patent_app_country] => US [patent_app_date] => 2006-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3614 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20070166917.pdf [firstpage_image] =>[orig_patent_app_number] => 11519655 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7545386 [patent_doc_number] => 08053357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-08 [patent_title] => 'Prevention of post CMP defects in CU/FSG process' [patent_app_type] => utility [patent_app_number] => 11/463515 [patent_app_country] => US [patent_app_date] => 2006-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 1859 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/053/08053357.pdf [firstpage_image] =>[orig_patent_app_number] => 11463515 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9875180 [patent_doc_number] => 08962447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'Bonded strained semiconductor with a desired surface orientation and conductance direction' [patent_app_type] => utility [patent_app_number] => 11/498586 [patent_app_country] => US [patent_app_date] => 2006-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 36 [patent_no_of_words] => 6924 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11498586 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 168281 [patent_doc_number] => 07666789 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-23 [patent_title] => 'Method of manufacturing a variable resistance structure and method of manufacturing a phase-change memory device using the same' [patent_app_type] => utility [patent_app_number] => 11/428925 [patent_app_country] => US [patent_app_date] => 2006-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 45 [patent_no_of_words] => 13478 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/666/07666789.pdf [firstpage_image] =>[orig_patent_app_number] => 11428925 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5602420 [patent_doc_number] => 20060292765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'Method for Making a FINFET Including a Superlattice' [patent_app_type] => utility [patent_app_number] => 11/426976 [patent_app_country] => US [patent_app_date] => 2006-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7929 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0292/20060292765.pdf [firstpage_image] =>[orig_patent_app_number] => 11426976 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5031682 [patent_doc_number] => 20070096221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'SEMICONDUCTOR DEVICE COMPRISING COPPER-BASED CONTACT PLUG AND A METHOD OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/427206 [patent_app_country] => US [patent_app_date] => 2006-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6289 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20070096221.pdf [firstpage_image] =>[orig_patent_app_number] => 11427206 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5136132 [patent_doc_number] => 20070077761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-05 [patent_title] => 'TECHNIQUE FOR FORMING A COPPER-BASED METALLIZATION LAYER INCLUDING A CONDUCTIVE CAPPING LAYER' [patent_app_type] => utility [patent_app_number] => 11/426346 [patent_app_country] => US [patent_app_date] => 2006-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7235 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20070077761.pdf [firstpage_image] =>[orig_patent_app_number] => 11426346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5196765 [patent_doc_number] => 20070296083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'Low dielectric constant integrated circuit insulators and methods' [patent_app_type] => utility [patent_app_number] => 11/471855 [patent_app_country] => US [patent_app_date] => 2006-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4894 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20070296083.pdf [firstpage_image] =>[orig_patent_app_number] => 11471855 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5196709 [patent_doc_number] => 20070296027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'CMOS DEVICES COMPRISING A CONTINUOUS STRESSOR LAYER WITH REGIONS OF OPPOSITE STRESSES, AND METHODS OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/425516 [patent_app_country] => US [patent_app_date] => 2006-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5114 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20070296027.pdf [firstpage_image] =>[orig_patent_app_number] => 11425516 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 224856 [patent_doc_number] => 07605039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-20 [patent_title] => 'Multiple-gate MOS transistor using Si substrate and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/447786 [patent_app_country] => US [patent_app_date] => 2006-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 6274 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/605/07605039.pdf [firstpage_image] =>[orig_patent_app_number] => 11447786 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5120124 [patent_doc_number] => 20070141838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Direct patterning method for manufacturing a metal layer of a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/441095 [patent_app_country] => US [patent_app_date] => 2006-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4196 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20070141838.pdf [firstpage_image] =>[orig_patent_app_number] => 11441095 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5069707 [patent_doc_number] => 20070190809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'Wafer processing method, semiconductor device manufacturing method, and wafer processing apparatus' [patent_app_type] => utility [patent_app_number] => 11/441065 [patent_app_country] => US [patent_app_date] => 2006-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5364 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20070190809.pdf [firstpage_image] =>[orig_patent_app_number] => 11441065 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5624784 [patent_doc_number] => 20060263289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'METAL OXIDE RESISTIVE MEMORY AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/419986 [patent_app_country] => US [patent_app_date] => 2006-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 8064 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20060263289.pdf [firstpage_image] =>[orig_patent_app_number] => 11419986 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5026299 [patent_doc_number] => 20070267745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-22 [patent_title] => 'Semiconductor device including electrically conductive bump and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/437726 [patent_app_country] => US [patent_app_date] => 2006-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2413 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20070267745.pdf [firstpage_image] =>[orig_patent_app_number] => 11437726 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5760239 [patent_doc_number] => 20060211184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-21 [patent_title] => 'Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique' [patent_app_type] => utility [patent_app_number] => 11/436756 [patent_app_country] => US [patent_app_date] => 2006-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6948 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20060211184.pdf [firstpage_image] =>[orig_patent_app_number] => 11436756 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5608627 [patent_doc_number] => 20060270143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'Method for manufacturing contact structures for dram semiconductor memories' [patent_app_type] => utility [patent_app_number] => 11/436376 [patent_app_country] => US [patent_app_date] => 2006-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4561 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20060270143.pdf [firstpage_image] =>[orig_patent_app_number] => 11436376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 803256 [patent_doc_number] => 07422960 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-09 [patent_title] => 'Method of forming gate arrays on a partial SOI substrate' [patent_app_type] => utility [patent_app_number] => 11/436726 [patent_app_country] => US [patent_app_date] => 2006-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 47 [patent_no_of_words] => 6963 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/422/07422960.pdf [firstpage_image] =>[orig_patent_app_number] => 11436726 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5625520 [patent_doc_number] => 20060264025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Stacked semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/434146 [patent_app_country] => US [patent_app_date] => 2006-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7105 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0264/20060264025.pdf [firstpage_image] =>[orig_patent_app_number] => 11434146 [rel_patent_id] =>[rel_patent_doc_number] =>)