Search

Dakota M Talbert

Examiner (ID: 4286)

Most Active Art Unit
2841
Art Unit(s)
2841
Total Applications
46
Issued Applications
8
Pending Applications
36
Abandoned Applications
2

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5046123 [patent_doc_number] => 20070264796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-15 [patent_title] => 'Method for forming a semiconductor on insulator structure' [patent_app_type] => utility [patent_app_number] => 11/433086 [patent_app_country] => US [patent_app_date] => 2006-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6823 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0264/20070264796.pdf [firstpage_image] =>[orig_patent_app_number] => 11433086 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/433086
Method for forming a semiconductor on insulator structure May 11, 2006 Abandoned
Array ( [id] => 5148878 [patent_doc_number] => 20070048938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Method of manufacturing MOS transistor with multiple channel structure' [patent_app_type] => utility [patent_app_number] => 11/431626 [patent_app_country] => US [patent_app_date] => 2006-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4401 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20070048938.pdf [firstpage_image] =>[orig_patent_app_number] => 11431626 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/431626
Method of manufacturing MOS transistor with multiple channel structure May 9, 2006 Abandoned
Array ( [id] => 5659060 [patent_doc_number] => 20060249656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'Manufacturing method for photoelectric package structure having two-layered substrate and control chip' [patent_app_type] => utility [patent_app_number] => 11/416156 [patent_app_country] => US [patent_app_date] => 2006-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2145 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20060249656.pdf [firstpage_image] =>[orig_patent_app_number] => 11416156 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/416156
Manufacturing method for photoelectric package structure having two-layered substrate and control chip May 2, 2006 Abandoned
Array ( [id] => 5250511 [patent_doc_number] => 20070131967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'Self-standing GaN single crystal substrate, method of making same, and method of making a nitride semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/413115 [patent_app_country] => US [patent_app_date] => 2006-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3460 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20070131967.pdf [firstpage_image] =>[orig_patent_app_number] => 11413115 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/413115
Self-standing GaN single crystal substrate, method of making same, and method of making a nitride semiconductor device Apr 27, 2006 Abandoned
Array ( [id] => 5659145 [patent_doc_number] => 20060249741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'GaN semiconductor devices with A1N buffer grown at high temperature and method for making the same' [patent_app_type] => utility [patent_app_number] => 11/410995 [patent_app_country] => US [patent_app_date] => 2006-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1277 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20060249741.pdf [firstpage_image] =>[orig_patent_app_number] => 11410995 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/410995
GaN semiconductor devices with A1N buffer grown at high temperature and method for making the same Apr 24, 2006 Abandoned
Array ( [id] => 4813425 [patent_doc_number] => 20080194056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'Method of Producing Plurality of Organic Transistors Using Laser Patterning' [patent_app_type] => utility [patent_app_number] => 11/910806 [patent_app_country] => US [patent_app_date] => 2006-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6127 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20080194056.pdf [firstpage_image] =>[orig_patent_app_number] => 11910806 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/910806
Method of producing plurality of organic transistors using laser patterning Apr 2, 2006 Issued
Array ( [id] => 5123578 [patent_doc_number] => 20070235848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'Substrate having conductive traces isolated by laser to allow electrical inspection' [patent_app_type] => utility [patent_app_number] => 11/392236 [patent_app_country] => US [patent_app_date] => 2006-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4163 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20070235848.pdf [firstpage_image] =>[orig_patent_app_number] => 11392236 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/392236
Substrate having conductive traces isolated by laser to allow electrical inspection Mar 28, 2006 Abandoned
Array ( [id] => 5060393 [patent_doc_number] => 20070222030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'LOW TEMPERATURE DEPOSITION AND ULTRA FAST ANNEALING OF INTEGRATED CIRCUIT THIN FILM CAPACITOR' [patent_app_type] => utility [patent_app_number] => 11/277606 [patent_app_country] => US [patent_app_date] => 2006-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5442 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20070222030.pdf [firstpage_image] =>[orig_patent_app_number] => 11277606 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/277606
Low temperature deposition and ultra fast annealing of integrated circuit thin film capacitor Mar 26, 2006 Issued
Array ( [id] => 8317437 [patent_doc_number] => 08232213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Semiconductor device and manufacturing method thereof, and liquid crystal display device' [patent_app_type] => utility [patent_app_number] => 11/816749 [patent_app_country] => US [patent_app_date] => 2006-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5754 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11816749 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/816749
Semiconductor device and manufacturing method thereof, and liquid crystal display device Mar 8, 2006 Issued
Array ( [id] => 7535664 [patent_doc_number] => 08049293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-01 [patent_title] => 'Solid-state image pickup device, electronic apparatus using such solid-state image pickup device and method of manufacturing solid-state image pickup device' [patent_app_type] => utility [patent_app_number] => 11/368756 [patent_app_country] => US [patent_app_date] => 2006-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 28 [patent_no_of_words] => 14600 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/049/08049293.pdf [firstpage_image] =>[orig_patent_app_number] => 11368756 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/368756
Solid-state image pickup device, electronic apparatus using such solid-state image pickup device and method of manufacturing solid-state image pickup device Mar 5, 2006 Issued
Array ( [id] => 5075381 [patent_doc_number] => 20070015356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-18 [patent_title] => 'Method for forming contact hole in semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/361525 [patent_app_country] => US [patent_app_date] => 2006-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2147 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20070015356.pdf [firstpage_image] =>[orig_patent_app_number] => 11361525 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/361525
Method for forming contact hole in semiconductor device Feb 23, 2006 Abandoned
Array ( [id] => 5688390 [patent_doc_number] => 20060286705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'Method of passivating compound semiconductor surfaces' [patent_app_type] => utility [patent_app_number] => 11/358606 [patent_app_country] => US [patent_app_date] => 2006-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4406 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0286/20060286705.pdf [firstpage_image] =>[orig_patent_app_number] => 11358606 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/358606
Method of passivating compound semiconductor surfaces Feb 20, 2006 Abandoned
Array ( [id] => 5113081 [patent_doc_number] => 20070196996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Semiconductor devices and methods of manufacturing thereof' [patent_app_type] => utility [patent_app_number] => 11/356666 [patent_app_country] => US [patent_app_date] => 2006-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6600 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20070196996.pdf [firstpage_image] =>[orig_patent_app_number] => 11356666 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/356666
CMOS devices having stress-altering material lining the isolation trenches and methods of manufacturing thereof Feb 16, 2006 Issued
Array ( [id] => 5069693 [patent_doc_number] => 20070190795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'Method for fabricating a semiconductor device with a high-K dielectric' [patent_app_type] => utility [patent_app_number] => 11/352565 [patent_app_country] => US [patent_app_date] => 2006-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3320 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20070190795.pdf [firstpage_image] =>[orig_patent_app_number] => 11352565 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/352565
Method for fabricating a semiconductor device with a high-K dielectric Feb 12, 2006 Abandoned
Array ( [id] => 295930 [patent_doc_number] => 07541199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-02 [patent_title] => 'Methods of forming magnetic memory devices including oxidizing and etching magnetic layers' [patent_app_type] => utility [patent_app_number] => 11/350545 [patent_app_country] => US [patent_app_date] => 2006-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5538 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/541/07541199.pdf [firstpage_image] =>[orig_patent_app_number] => 11350545 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/350545
Methods of forming magnetic memory devices including oxidizing and etching magnetic layers Feb 8, 2006 Issued
Array ( [id] => 583731 [patent_doc_number] => 07446026 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'Method of forming a CMOS device with stressor source/drain regions' [patent_app_type] => utility [patent_app_number] => 11/349595 [patent_app_country] => US [patent_app_date] => 2006-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4140 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/446/07446026.pdf [firstpage_image] =>[orig_patent_app_number] => 11349595 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/349595
Method of forming a CMOS device with stressor source/drain regions Feb 7, 2006 Issued
Array ( [id] => 5101368 [patent_doc_number] => 20070184630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Method of bonding a semiconductor wafer to a support substrate' [patent_app_type] => utility [patent_app_number] => 11/349566 [patent_app_country] => US [patent_app_date] => 2006-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1189 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20070184630.pdf [firstpage_image] =>[orig_patent_app_number] => 11349566 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/349566
Method of bonding a semiconductor wafer to a support substrate Feb 7, 2006 Abandoned
Array ( [id] => 5101390 [patent_doc_number] => 20070184652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Method for preparing a metal feature surface prior to electroless metal deposition' [patent_app_type] => utility [patent_app_number] => 11/349355 [patent_app_country] => US [patent_app_date] => 2006-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3222 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20070184652.pdf [firstpage_image] =>[orig_patent_app_number] => 11349355 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/349355
Method for preparing a metal feature surface prior to electroless metal deposition Feb 6, 2006 Abandoned
Array ( [id] => 177841 [patent_doc_number] => 07655549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-02 [patent_title] => 'Method for depositing a metal gate on a high-k dielectric film' [patent_app_type] => utility [patent_app_number] => 11/347256 [patent_app_country] => US [patent_app_date] => 2006-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8110 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 403 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/655/07655549.pdf [firstpage_image] =>[orig_patent_app_number] => 11347256 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/347256
Method for depositing a metal gate on a high-k dielectric film Feb 5, 2006 Issued
Array ( [id] => 5177573 [patent_doc_number] => 20070178633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'Semiconductor device comprising a transistor having a counter-doped channel region and method for forming the same' [patent_app_type] => utility [patent_app_number] => 11/342025 [patent_app_country] => US [patent_app_date] => 2006-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4980 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20070178633.pdf [firstpage_image] =>[orig_patent_app_number] => 11342025 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/342025
Semiconductor device comprising a transistor having a counter-doped channel region and method for forming the same Jan 26, 2006 Issued
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