Dakota M Talbert
Examiner (ID: 4286)
Most Active Art Unit | 2841 |
Art Unit(s) | 2841 |
Total Applications | 46 |
Issued Applications | 8 |
Pending Applications | 36 |
Abandoned Applications | 2 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 5874614
[patent_doc_number] => 20060166494
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-27
[patent_title] => 'Method of manufacturing a semiconductor device that includes a contact plug'
[patent_app_type] => utility
[patent_app_number] => 11/335215
[patent_app_country] => US
[patent_app_date] => 2006-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5465
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0166/20060166494.pdf
[firstpage_image] =>[orig_patent_app_number] => 11335215
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/335215 | Method of manufacturing a semiconductor device that includes a contact plug | Jan 17, 2006 | Abandoned |
Array
(
[id] => 4971427
[patent_doc_number] => 20070111429
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-17
[patent_title] => 'Method of manufacturing a pipe shaped phase change memory'
[patent_app_type] => utility
[patent_app_number] => 11/333156
[patent_app_country] => US
[patent_app_date] => 2006-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5677
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0111/20070111429.pdf
[firstpage_image] =>[orig_patent_app_number] => 11333156
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/333156 | Method of manufacturing a pipe shaped phase change memory | Jan 16, 2006 | Abandoned |
Array
(
[id] => 5186059
[patent_doc_number] => 20070164366
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-19
[patent_title] => 'Mitigation of gate oxide thinning in dual gate CMOS process technology'
[patent_app_type] => utility
[patent_app_number] => 11/331505
[patent_app_country] => US
[patent_app_date] => 2006-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4235
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0164/20070164366.pdf
[firstpage_image] =>[orig_patent_app_number] => 11331505
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/331505 | Mitigation of gate oxide thinning in dual gate CMOS process technology | Jan 12, 2006 | Abandoned |
Array
(
[id] => 5217454
[patent_doc_number] => 20070158765
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-12
[patent_title] => 'Gallium lanthanide oxide films'
[patent_app_type] => utility
[patent_app_number] => 11/329025
[patent_app_country] => US
[patent_app_date] => 2006-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 10780
[patent_no_of_claims] => 87
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0158/20070158765.pdf
[firstpage_image] =>[orig_patent_app_number] => 11329025
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/329025 | Gallium lanthanide oxide films | Jan 9, 2006 | Issued |
Array
(
[id] => 5034878
[patent_doc_number] => 20070099417
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-03
[patent_title] => 'Adhesion and minimizing oxidation on electroless CO alloy films for integration with low K inter-metal dielectric and etch stop'
[patent_app_type] => utility
[patent_app_number] => 11/329785
[patent_app_country] => US
[patent_app_date] => 2006-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3684
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0099/20070099417.pdf
[firstpage_image] =>[orig_patent_app_number] => 11329785
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/329785 | Adhesion and minimizing oxidation on electroless CO alloy films for integration with low K inter-metal dielectric and etch stop | Jan 9, 2006 | Abandoned |
Array
(
[id] => 813696
[patent_doc_number] => 07413968
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-08-19
[patent_title] => 'Method of manufacturing semiconductor device having gate electrodes of polymetal gate and dual-gate structure'
[patent_app_type] => utility
[patent_app_number] => 11/328225
[patent_app_country] => US
[patent_app_date] => 2006-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 25
[patent_no_of_words] => 4513
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/413/07413968.pdf
[firstpage_image] =>[orig_patent_app_number] => 11328225
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/328225 | Method of manufacturing semiconductor device having gate electrodes of polymetal gate and dual-gate structure | Jan 9, 2006 | Issued |
Array
(
[id] => 4985928
[patent_doc_number] => 20070152266
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-05
[patent_title] => 'Method and structure for reducing the external resistance of a three-dimensional transistor through use of epitaxial layers'
[patent_app_type] => utility
[patent_app_number] => 11/322795
[patent_app_country] => US
[patent_app_date] => 2005-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2225
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0152/20070152266.pdf
[firstpage_image] =>[orig_patent_app_number] => 11322795
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/322795 | Method and structure for reducing the external resistance of a three-dimensional transistor through use of epitaxial layers | Dec 28, 2005 | Abandoned |
Array
(
[id] => 250748
[patent_doc_number] => 07582504
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-09-01
[patent_title] => 'CMOS image sensor and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/319596
[patent_app_country] => US
[patent_app_date] => 2005-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 16
[patent_no_of_words] => 2295
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/582/07582504.pdf
[firstpage_image] =>[orig_patent_app_number] => 11319596
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/319596 | CMOS image sensor and method for manufacturing the same | Dec 28, 2005 | Issued |
Array
(
[id] => 5141885
[patent_doc_number] => 20070004101
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-04
[patent_title] => 'Manufacturing method of array substrate using lift-off method'
[patent_app_type] => utility
[patent_app_number] => 11/319306
[patent_app_country] => US
[patent_app_date] => 2005-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 4521
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0004/20070004101.pdf
[firstpage_image] =>[orig_patent_app_number] => 11319306
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/319306 | Manufacturing method of array substrate using lift-off method | Dec 26, 2005 | Issued |
Array
(
[id] => 4544401
[patent_doc_number] => 07889557
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-02-15
[patent_title] => 'NAND flash memory device with increased spacing between selection transistors and adjacent memory cells'
[patent_app_type] => utility
[patent_app_number] => 11/315395
[patent_app_country] => US
[patent_app_date] => 2005-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 5367
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/889/07889557.pdf
[firstpage_image] =>[orig_patent_app_number] => 11315395
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/315395 | NAND flash memory device with increased spacing between selection transistors and adjacent memory cells | Dec 20, 2005 | Issued |
Array
(
[id] => 5233852
[patent_doc_number] => 20070126007
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-07
[patent_title] => 'SiC semiconductor device and method of fabricating same'
[patent_app_type] => utility
[patent_app_number] => 11/295915
[patent_app_country] => US
[patent_app_date] => 2005-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3132
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0126/20070126007.pdf
[firstpage_image] =>[orig_patent_app_number] => 11295915
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/295915 | SiC semiconductor device and method of fabricating same | Dec 6, 2005 | Abandoned |
Array
(
[id] => 7692065
[patent_doc_number] => 20070231968
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-04
[patent_title] => 'Method for Producing an Electronic Circuit'
[patent_app_type] => utility
[patent_app_number] => 11/575586
[patent_app_country] => US
[patent_app_date] => 2005-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2328
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0231/20070231968.pdf
[firstpage_image] =>[orig_patent_app_number] => 11575586
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/575586 | Method for producing an electronic circuit | Nov 27, 2005 | Issued |
Array
(
[id] => 5634920
[patent_doc_number] => 20060065893
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-30
[patent_title] => 'Method of forming gate by using layer-growing process and gate structure manufactured thereby'
[patent_app_type] => utility
[patent_app_number] => 11/233806
[patent_app_country] => US
[patent_app_date] => 2005-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4970
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0065/20060065893.pdf
[firstpage_image] =>[orig_patent_app_number] => 11233806
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/233806 | Method of forming gate by using layer-growing process and gate structure manufactured thereby | Sep 22, 2005 | Abandoned |
Array
(
[id] => 15889371
[patent_doc_number] => 10651037
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-05-12
[patent_title] => Method for fabricating a doped zone in a semiconductor body
[patent_app_type] => utility
[patent_app_number] => 11/232735
[patent_app_country] => US
[patent_app_date] => 2005-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 24
[patent_no_of_words] => 9687
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 237
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11232735
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/232735 | Method for fabricating a doped zone in a semiconductor body | Sep 21, 2005 | Issued |
Array
(
[id] => 326587
[patent_doc_number] => 07514358
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-04-07
[patent_title] => 'Sequential deposition of tantalum nitride using a tantalum-containing precursor and a nitrogen-containing precursor'
[patent_app_type] => utility
[patent_app_number] => 11/231386
[patent_app_country] => US
[patent_app_date] => 2005-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 5881
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/514/07514358.pdf
[firstpage_image] =>[orig_patent_app_number] => 11231386
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/231386 | Sequential deposition of tantalum nitride using a tantalum-containing precursor and a nitrogen-containing precursor | Sep 20, 2005 | Issued |
Array
(
[id] => 5708102
[patent_doc_number] => 20060049446
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-09
[patent_title] => 'Method for manufacturing a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/229685
[patent_app_country] => US
[patent_app_date] => 2005-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 3600
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0049/20060049446.pdf
[firstpage_image] =>[orig_patent_app_number] => 11229685
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/229685 | Method of forming a contact hole in a semiconductor device | Sep 19, 2005 | Issued |
Array
(
[id] => 5107182
[patent_doc_number] => 20070066060
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-22
[patent_title] => 'Semiconductor devices and fabrication methods thereof'
[patent_app_type] => utility
[patent_app_number] => 11/230125
[patent_app_country] => US
[patent_app_date] => 2005-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2636
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0066/20070066060.pdf
[firstpage_image] =>[orig_patent_app_number] => 11230125
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/230125 | Semiconductor devices and fabrication methods thereof | Sep 18, 2005 | Abandoned |
Array
(
[id] => 5823665
[patent_doc_number] => 20060060847
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-23
[patent_title] => 'Silicon-insulator-silicon structure and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/228225
[patent_app_country] => US
[patent_app_date] => 2005-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1961
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0060/20060060847.pdf
[firstpage_image] =>[orig_patent_app_number] => 11228225
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/228225 | Silicon-insulator-silicon structure and method for fabricating the same | Sep 18, 2005 | Abandoned |
Array
(
[id] => 260016
[patent_doc_number] => 07572741
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-08-11
[patent_title] => 'Methods of fabricating oxide layers on silicon carbide layers utilizing atomic oxygen'
[patent_app_type] => utility
[patent_app_number] => 11/229476
[patent_app_country] => US
[patent_app_date] => 2005-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 14
[patent_no_of_words] => 7334
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/572/07572741.pdf
[firstpage_image] =>[orig_patent_app_number] => 11229476
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/229476 | Methods of fabricating oxide layers on silicon carbide layers utilizing atomic oxygen | Sep 15, 2005 | Issued |
Array
(
[id] => 5107143
[patent_doc_number] => 20070066021
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-22
[patent_title] => 'Formation of gate dielectrics with uniform nitrogen distribution'
[patent_app_type] => utility
[patent_app_number] => 11/229115
[patent_app_country] => US
[patent_app_date] => 2005-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3410
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0066/20070066021.pdf
[firstpage_image] =>[orig_patent_app_number] => 11229115
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/229115 | Formation of gate dielectrics with uniform nitrogen distribution | Sep 15, 2005 | Abandoned |