Search

Dakota M Talbert

Examiner (ID: 4286)

Most Active Art Unit
2841
Art Unit(s)
2841
Total Applications
46
Issued Applications
8
Pending Applications
36
Abandoned Applications
2

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5642755 [patent_doc_number] => 20060281210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-14 [patent_title] => 'Semiconductor device manufacturing method' [patent_app_type] => utility [patent_app_number] => 11/224996 [patent_app_country] => US [patent_app_date] => 2005-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7886 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20060281210.pdf [firstpage_image] =>[orig_patent_app_number] => 11224996 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/224996
Semiconductor device manufacturing method Sep 13, 2005 Abandoned
Array ( [id] => 5056969 [patent_doc_number] => 20070059891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Mandrel/trim alignment in SIT processing' [patent_app_type] => utility [patent_app_number] => 11/226726 [patent_app_country] => US [patent_app_date] => 2005-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7563 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20070059891.pdf [firstpage_image] =>[orig_patent_app_number] => 11226726 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/226726
Mandrel/trim alignment in SIT processing Sep 13, 2005 Issued
Array ( [id] => 5793629 [patent_doc_number] => 20060014310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-19 [patent_title] => 'Resonant cavity III-nitride light emitting devices fabricated by growth substrate removal' [patent_app_type] => utility [patent_app_number] => 11/227416 [patent_app_country] => US [patent_app_date] => 2005-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5171 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20060014310.pdf [firstpage_image] =>[orig_patent_app_number] => 11227416 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/227416
Resonant cavity III-nitride light emitting devices fabricated by growth substrate removal Sep 13, 2005 Abandoned
Array ( [id] => 4624174 [patent_doc_number] => 08003470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Strained semiconductor device and method of making the same' [patent_app_type] => utility [patent_app_number] => 11/224825 [patent_app_country] => US [patent_app_date] => 2005-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 4428 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/003/08003470.pdf [firstpage_image] =>[orig_patent_app_number] => 11224825 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/224825
Strained semiconductor device and method of making the same Sep 12, 2005 Issued
Array ( [id] => 132632 [patent_doc_number] => 07696065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-13 [patent_title] => 'Method of manufacturing a semiconductor device by forming separation regions which do not extend to the peripherals of a substrate, and structures thereof' [patent_app_type] => utility [patent_app_number] => 11/222895 [patent_app_country] => US [patent_app_date] => 2005-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 10294 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/696/07696065.pdf [firstpage_image] =>[orig_patent_app_number] => 11222895 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/222895
Method of manufacturing a semiconductor device by forming separation regions which do not extend to the peripherals of a substrate, and structures thereof Sep 7, 2005 Issued
Array ( [id] => 5708204 [patent_doc_number] => 20060049548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-09 [patent_title] => 'Method for producing an optical or electronic module provided with a plastic package and an optical or electronic module' [patent_app_type] => utility [patent_app_number] => 11/216565 [patent_app_country] => US [patent_app_date] => 2005-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3633 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20060049548.pdf [firstpage_image] =>[orig_patent_app_number] => 11216565 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/216565
Method for producing an optical or electronic module provided with a plastic package and an optical or electronic module Aug 30, 2005 Abandoned
Array ( [id] => 5619493 [patent_doc_number] => 20060189027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Method of fabricating avalanche photodiode' [patent_app_type] => utility [patent_app_number] => 11/215905 [patent_app_country] => US [patent_app_date] => 2005-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2093 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20060189027.pdf [firstpage_image] =>[orig_patent_app_number] => 11215905 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/215905
Method of fabricating avalanche photodiode Aug 30, 2005 Abandoned
Array ( [id] => 5619486 [patent_doc_number] => 20060189020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Method for manufacturing nitride based single crystal substrate and method for manufacturing nitride based light emitting diode using the same' [patent_app_type] => utility [patent_app_number] => 11/214685 [patent_app_country] => US [patent_app_date] => 2005-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3866 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20060189020.pdf [firstpage_image] =>[orig_patent_app_number] => 11214685 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/214685
Method for manufacturing nitride based single crystal substrate and method for manufacturing nitride based light emitting diode using the same Aug 29, 2005 Abandoned
Array ( [id] => 5148832 [patent_doc_number] => 20070048892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Encapsulating electrode' [patent_app_type] => utility [patent_app_number] => 11/211656 [patent_app_country] => US [patent_app_date] => 2005-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8997 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20070048892.pdf [firstpage_image] =>[orig_patent_app_number] => 11211656 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/211656
Method of forming an encapsulating electrode Aug 25, 2005 Issued
Array ( [id] => 5148902 [patent_doc_number] => 20070048962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'TaN integrated circuit (IC) capacitor formation' [patent_app_type] => utility [patent_app_number] => 11/212456 [patent_app_country] => US [patent_app_date] => 2005-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4087 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20070048962.pdf [firstpage_image] =>[orig_patent_app_number] => 11212456 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/212456
TaN integrated circuit (IC) capacitor formation Aug 25, 2005 Abandoned
Array ( [id] => 5894977 [patent_doc_number] => 20060003516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Flash memory devices on silicon carbide' [patent_app_type] => utility [patent_app_number] => 11/211206 [patent_app_country] => US [patent_app_date] => 2005-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2092 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20060003516.pdf [firstpage_image] =>[orig_patent_app_number] => 11211206 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/211206
Flash memory devices on silicon carbide Aug 24, 2005 Abandoned
Array ( [id] => 5183120 [patent_doc_number] => 20070054474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-08 [patent_title] => 'Crack-free III-V epitaxy on germanium on insulator (GOI) substrates' [patent_app_type] => utility [patent_app_number] => 11/209295 [patent_app_country] => US [patent_app_date] => 2005-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4886 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20070054474.pdf [firstpage_image] =>[orig_patent_app_number] => 11209295 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/209295
Crack-free III-V epitaxy on germanium on insulator (GOI) substrates Aug 22, 2005 Abandoned
Array ( [id] => 5183095 [patent_doc_number] => 20070054449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-08 [patent_title] => 'Methods of forming charge-trapping dielectric layers for semiconductor memory devices' [patent_app_type] => utility [patent_app_number] => 11/209875 [patent_app_country] => US [patent_app_date] => 2005-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4284 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20070054449.pdf [firstpage_image] =>[orig_patent_app_number] => 11209875 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/209875
Methods of forming charge-trapping dielectric layers for semiconductor memory devices Aug 22, 2005 Issued
Array ( [id] => 887915 [patent_doc_number] => 07348233 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-03-25 [patent_title] => 'Methods for fabricating a CMOS device including silicide contacts' [patent_app_type] => utility [patent_app_number] => 11/207265 [patent_app_country] => US [patent_app_date] => 2005-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3551 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/348/07348233.pdf [firstpage_image] =>[orig_patent_app_number] => 11207265 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/207265
Methods for fabricating a CMOS device including silicide contacts Aug 18, 2005 Issued
Array ( [id] => 4997531 [patent_doc_number] => 20070040165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Method of fabricating organic FETs' [patent_app_type] => utility [patent_app_number] => 11/204725 [patent_app_country] => US [patent_app_date] => 2005-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4686 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20070040165.pdf [firstpage_image] =>[orig_patent_app_number] => 11204725 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/204725
Method of fabricating organic FETs Aug 15, 2005 Abandoned
Array ( [id] => 4688330 [patent_doc_number] => 20080032511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'Semiconductor Device Manufacturing Method and Plasma Oxidation Treatment Method' [patent_app_type] => utility [patent_app_number] => 11/573586 [patent_app_country] => US [patent_app_date] => 2005-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12045 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20080032511.pdf [firstpage_image] =>[orig_patent_app_number] => 11573586 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/573586
Semiconductor device manufacturing method and plasma oxidation treatment method Aug 10, 2005 Issued
Array ( [id] => 895031 [patent_doc_number] => 07341920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-11 [patent_title] => 'Method for forming a bipolar transistor device with self-aligned raised extrinsic base' [patent_app_type] => utility [patent_app_number] => 11/160706 [patent_app_country] => US [patent_app_date] => 2005-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 5678 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/341/07341920.pdf [firstpage_image] =>[orig_patent_app_number] => 11160706 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/160706
Method for forming a bipolar transistor device with self-aligned raised extrinsic base Jul 5, 2005 Issued
Array ( [id] => 5141878 [patent_doc_number] => 20070004094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'Method of reducing warpage in an over-molded IC package' [patent_app_type] => utility [patent_app_number] => 11/171095 [patent_app_country] => US [patent_app_date] => 2005-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5888 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20070004094.pdf [firstpage_image] =>[orig_patent_app_number] => 11171095 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/171095
Method of reducing warpage in an over-molded IC package Jun 29, 2005 Abandoned
Array ( [id] => 4666457 [patent_doc_number] => 20080041517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'Assembling Two Substrates by Molecular Adhesion, One of the Two Supporting an Electrically Conductive Film' [patent_app_type] => utility [patent_app_number] => 11/630033 [patent_app_country] => US [patent_app_date] => 2005-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6583 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20080041517.pdf [firstpage_image] =>[orig_patent_app_number] => 11630033 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/630033
Assembling Two Substrates by Molecular Adhesion, One of the Two Supporting an Electrically Conductive Film Jun 28, 2005 Abandoned
Array ( [id] => 5599655 [patent_doc_number] => 20060290000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'Composite metal layer formed using metal nanocrystalline particles in an electroplating bath' [patent_app_type] => utility [patent_app_number] => 11/169596 [patent_app_country] => US [patent_app_date] => 2005-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3593 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0290/20060290000.pdf [firstpage_image] =>[orig_patent_app_number] => 11169596 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/169596
Composite metal layer formed using metal nanocrystalline particles in an electroplating bath Jun 27, 2005 Abandoned
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