Dakota M Talbert
Examiner (ID: 4286)
Most Active Art Unit | 2841 |
Art Unit(s) | 2841 |
Total Applications | 46 |
Issued Applications | 8 |
Pending Applications | 36 |
Abandoned Applications | 2 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 345014
[patent_doc_number] => 07498201
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-03-03
[patent_title] => 'Method of forming a multi-die semiconductor package'
[patent_app_type] => utility
[patent_app_number] => 11/167495
[patent_app_country] => US
[patent_app_date] => 2005-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 1939
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/498/07498201.pdf
[firstpage_image] =>[orig_patent_app_number] => 11167495
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/167495 | Method of forming a multi-die semiconductor package | Jun 26, 2005 | Issued |
Array
(
[id] => 557350
[patent_doc_number] => 07470575
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-12-30
[patent_title] => 'Process for fabricating semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/165235
[patent_app_country] => US
[patent_app_date] => 2005-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 34
[patent_no_of_words] => 17085
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/470/07470575.pdf
[firstpage_image] =>[orig_patent_app_number] => 11165235
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/165235 | Process for fabricating semiconductor device | Jun 23, 2005 | Issued |
Array
(
[id] => 7965939
[patent_doc_number] => 07939440
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-10
[patent_title] => 'Junction leakage suppression in memory devices'
[patent_app_type] => utility
[patent_app_number] => 11/152375
[patent_app_country] => US
[patent_app_date] => 2005-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 4221
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 364
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/939/07939440.pdf
[firstpage_image] =>[orig_patent_app_number] => 11152375
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/152375 | Junction leakage suppression in memory devices | Jun 14, 2005 | Issued |
Array
(
[id] => 5785588
[patent_doc_number] => 20060205149
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-09-14
[patent_title] => 'Method of fabricating flash memory device'
[patent_app_type] => utility
[patent_app_number] => 11/151016
[patent_app_country] => US
[patent_app_date] => 2005-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2836
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0205/20060205149.pdf
[firstpage_image] =>[orig_patent_app_number] => 11151016
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/151016 | Method of fabricating flash memory device | Jun 12, 2005 | Abandoned |
Array
(
[id] => 5763164
[patent_doc_number] => 20060017103
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-26
[patent_title] => 'Method for making reduced size DMOS transistor and resulting DMOS transistor'
[patent_app_type] => utility
[patent_app_number] => 11/146306
[patent_app_country] => US
[patent_app_date] => 2005-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2952
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0017/20060017103.pdf
[firstpage_image] =>[orig_patent_app_number] => 11146306
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/146306 | Method for making reduced size DMOS transistor and resulting DMOS transistor | Jun 5, 2005 | Abandoned |
Array
(
[id] => 5767965
[patent_doc_number] => 20060019423
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-26
[patent_title] => 'Method for manufacturing solid-state image sensor'
[patent_app_type] => utility
[patent_app_number] => 11/145675
[patent_app_country] => US
[patent_app_date] => 2005-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 5216
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0019/20060019423.pdf
[firstpage_image] =>[orig_patent_app_number] => 11145675
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/145675 | Method for manufacturing solid-state image sensor | Jun 5, 2005 | Abandoned |
Array
(
[id] => 7069630
[patent_doc_number] => 20050245015
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-03
[patent_title] => 'Method for manufacturing a semiconductor device having a dual-gate structure'
[patent_app_type] => utility
[patent_app_number] => 11/116445
[patent_app_country] => US
[patent_app_date] => 2005-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4893
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0245/20050245015.pdf
[firstpage_image] =>[orig_patent_app_number] => 11116445
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/116445 | Method for manufacturing a semiconductor device having a dual-gate structure | Apr 27, 2005 | Abandoned |
Array
(
[id] => 5743242
[patent_doc_number] => 20060088967
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-27
[patent_title] => 'Finfet transistor process'
[patent_app_type] => utility
[patent_app_number] => 11/114735
[patent_app_country] => US
[patent_app_date] => 2005-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 2637
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0088/20060088967.pdf
[firstpage_image] =>[orig_patent_app_number] => 11114735
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/114735 | Finfet transistor process | Apr 25, 2005 | Abandoned |
Array
(
[id] => 7049495
[patent_doc_number] => 20050185382
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-25
[patent_title] => 'Substrate for carrying a semiconductor chip and a manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/112343
[patent_app_country] => US
[patent_app_date] => 2005-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6509
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0185/20050185382.pdf
[firstpage_image] =>[orig_patent_app_number] => 11112343
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/112343 | Substrate for carrying a semiconductor chip and a manufacturing method thereof | Apr 21, 2005 | Abandoned |
Array
(
[id] => 6926012
[patent_doc_number] => 20050239267
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-27
[patent_title] => 'Substrate manufacturing method'
[patent_app_type] => utility
[patent_app_number] => 11/110666
[patent_app_country] => US
[patent_app_date] => 2005-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6916
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0239/20050239267.pdf
[firstpage_image] =>[orig_patent_app_number] => 11110666
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/110666 | Substrate manufacturing method | Apr 20, 2005 | Abandoned |
Array
(
[id] => 847147
[patent_doc_number] => 07384847
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-06-10
[patent_title] => 'Methods of forming DRAM arrays'
[patent_app_type] => utility
[patent_app_number] => 11/111625
[patent_app_country] => US
[patent_app_date] => 2005-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 40
[patent_figures_cnt] => 42
[patent_no_of_words] => 9161
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 262
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/384/07384847.pdf
[firstpage_image] =>[orig_patent_app_number] => 11111625
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/111625 | Methods of forming DRAM arrays | Apr 20, 2005 | Issued |
Array
(
[id] => 5754091
[patent_doc_number] => 20060223240
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-05
[patent_title] => 'Method of making substrate for integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/109785
[patent_app_country] => US
[patent_app_date] => 2005-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1245
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0223/20060223240.pdf
[firstpage_image] =>[orig_patent_app_number] => 11109785
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/109785 | Method of making substrate for integrated circuit | Apr 19, 2005 | Abandoned |
Array
(
[id] => 5851307
[patent_doc_number] => 20060234498
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-19
[patent_title] => 'Method of performing a surface treatment respectively on the via and the trench in a dual damascene process'
[patent_app_type] => utility
[patent_app_number] => 11/107966
[patent_app_country] => US
[patent_app_date] => 2005-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 1605
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0234/20060234498.pdf
[firstpage_image] =>[orig_patent_app_number] => 11107966
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/107966 | Method of performing a surface treatment respectively on the via and the trench in a dual damascene process | Apr 17, 2005 | Abandoned |
Array
(
[id] => 7185588
[patent_doc_number] => 20050191824
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-01
[patent_title] => 'Methods for producing a multilayer semiconductor structure'
[patent_app_type] => utility
[patent_app_number] => 11/106135
[patent_app_country] => US
[patent_app_date] => 2005-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 4203
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0191/20050191824.pdf
[firstpage_image] =>[orig_patent_app_number] => 11106135
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/106135 | Methods for producing a multilayer semiconductor structure | Apr 12, 2005 | Issued |
Array
(
[id] => 5851311
[patent_doc_number] => 20060234502
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-19
[patent_title] => 'Method of forming titanium nitride layers'
[patent_app_type] => utility
[patent_app_number] => 11/105096
[patent_app_country] => US
[patent_app_date] => 2005-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3792
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0234/20060234502.pdf
[firstpage_image] =>[orig_patent_app_number] => 11105096
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/105096 | Method of forming titanium nitride layers | Apr 12, 2005 | Abandoned |
Array
(
[id] => 5619489
[patent_doc_number] => 20060189023
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-24
[patent_title] => 'Three dimensional structure formed by using an adhesive silicon wafer process'
[patent_app_type] => utility
[patent_app_number] => 11/064985
[patent_app_country] => US
[patent_app_date] => 2005-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2812
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0189/20060189023.pdf
[firstpage_image] =>[orig_patent_app_number] => 11064985
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/064985 | Three dimensional structure formed by using an adhesive silicon wafer process | Feb 22, 2005 | Abandoned |
Array
(
[id] => 7050856
[patent_doc_number] => 20050186743
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-25
[patent_title] => 'Method for manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/061466
[patent_app_country] => US
[patent_app_date] => 2005-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 9130
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0186/20050186743.pdf
[firstpage_image] =>[orig_patent_app_number] => 11061466
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/061466 | Method for manufacturing semiconductor device | Feb 21, 2005 | Abandoned |
Array
(
[id] => 840375
[patent_doc_number] => 07390703
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-06-24
[patent_title] => 'Method for through-plating field effect transistors with a self-assembled monolayer of an organic compound as gate dielectric'
[patent_app_type] => utility
[patent_app_number] => 11/062766
[patent_app_country] => US
[patent_app_date] => 2005-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 2534
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/390/07390703.pdf
[firstpage_image] =>[orig_patent_app_number] => 11062766
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/062766 | Method for through-plating field effect transistors with a self-assembled monolayer of an organic compound as gate dielectric | Feb 21, 2005 | Issued |
Array
(
[id] => 322583
[patent_doc_number] => 07517816
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-04-14
[patent_title] => 'Technique for creating different mechanical stress in different channel regions by forming an etch stop layer having differently modified intrinsic stress'
[patent_app_type] => utility
[patent_app_number] => 11/058035
[patent_app_country] => US
[patent_app_date] => 2005-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 24
[patent_no_of_words] => 8005
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/517/07517816.pdf
[firstpage_image] =>[orig_patent_app_number] => 11058035
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/058035 | Technique for creating different mechanical stress in different channel regions by forming an etch stop layer having differently modified intrinsic stress | Feb 14, 2005 | Issued |
Array
(
[id] => 6963361
[patent_doc_number] => 20050230258
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-20
[patent_title] => 'Apparatus and process for sensing fluoro species in semiconductor processing systems'
[patent_app_type] => utility
[patent_app_number] => 11/057735
[patent_app_country] => US
[patent_app_date] => 2005-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 13752
[patent_no_of_claims] => 50
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0230/20050230258.pdf
[firstpage_image] =>[orig_patent_app_number] => 11057735
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/057735 | Apparatus and process for sensing fluoro species in semiconductor processing systems | Feb 13, 2005 | Abandoned |