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Dakota M Talbert

Examiner (ID: 4286)

Most Active Art Unit
2841
Art Unit(s)
2841
Total Applications
46
Issued Applications
8
Pending Applications
36
Abandoned Applications
2

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17262794 [patent_doc_number] => 20210375779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/885278 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4864 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16885278 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/885278
Damascene process using cap layer May 27, 2020 Issued
Array ( [id] => 16286379 [patent_doc_number] => 20200279981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-03 [patent_title] => METHOD OF MANUFACTURING LIGHT EMITTING DEVICE [patent_app_type] => utility [patent_app_number] => 16/878241 [patent_app_country] => US [patent_app_date] => 2020-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6583 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16878241 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/878241
Method for attaching light transmissive member to light emitting element May 18, 2020 Issued
Array ( [id] => 17247020 [patent_doc_number] => 20210366765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => VIA STRUCTURE AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/877670 [patent_app_country] => US [patent_app_date] => 2020-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16877670 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/877670
Via structure and methods for forming the same May 18, 2020 Issued
Array ( [id] => 16257015 [patent_doc_number] => 20200266390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => ORGANIC LIGHT EMITTING DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/868217 [patent_app_country] => US [patent_app_date] => 2020-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9095 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16868217 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/868217
Organic light emitting display device May 5, 2020 Issued
Array ( [id] => 16256790 [patent_doc_number] => 20200266165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => COPPER PILLARS HAVING IMPROVED INTEGRITY AND METHODS OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 16/866709 [patent_app_country] => US [patent_app_date] => 2020-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9032 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16866709 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/866709
COPPER PILLARS HAVING IMPROVED INTEGRITY AND METHODS OF MAKING THE SAME May 4, 2020 Abandoned
Array ( [id] => 16241640 [patent_doc_number] => 20200258874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => ISOLATOR INTEGRATED CIRCUITS WITH PACKAGE STRUCTURE CAVITY AND FABRICATION METHODS [patent_app_type] => utility [patent_app_number] => 16/859345 [patent_app_country] => US [patent_app_date] => 2020-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 491 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16859345 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/859345
Isolator integrated circuits with package structure cavity and fabrication methods Apr 26, 2020 Issued
Array ( [id] => 17156529 [patent_doc_number] => 20210317580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => METHOD OF DIELECTRIC MATERIAL FILL AND TREATMENT [patent_app_type] => utility [patent_app_number] => 16/848784 [patent_app_country] => US [patent_app_date] => 2020-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16848784 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/848784
Method of dielectric material fill and treatment Apr 13, 2020 Issued
Array ( [id] => 17517011 [patent_doc_number] => 11296172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/842862 [patent_app_country] => US [patent_app_date] => 2020-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6535 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16842862 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/842862
Semiconductor device Apr 7, 2020 Issued
Array ( [id] => 17115575 [patent_doc_number] => 20210296172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => FULLY ALIGNED INTERCONNECTS WITH SELECTIVE AREA DEPOSITION [patent_app_type] => utility [patent_app_number] => 16/826566 [patent_app_country] => US [patent_app_date] => 2020-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4872 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16826566 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/826566
Fully aligned interconnects with selective area deposition Mar 22, 2020 Issued
Array ( [id] => 17070627 [patent_doc_number] => 20210272844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/807138 [patent_app_country] => US [patent_app_date] => 2020-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3216 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16807138 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/807138
Liner for through-silicon via Mar 1, 2020 Issued
Array ( [id] => 17025432 [patent_doc_number] => 20210249304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => Conductive Interconnects and Methods of Forming Conductive Interconnects [patent_app_type] => utility [patent_app_number] => 16/787321 [patent_app_country] => US [patent_app_date] => 2020-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16787321 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/787321
Conductive interconnects and methods of forming conductive interconnects Feb 10, 2020 Issued
Array ( [id] => 17668285 [patent_doc_number] => 11361989 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-14 [patent_title] => Method for manufacturing interconnect structures including air gaps [patent_app_type] => utility [patent_app_number] => 16/788057 [patent_app_country] => US [patent_app_date] => 2020-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6872 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16788057 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/788057
Method for manufacturing interconnect structures including air gaps Feb 10, 2020 Issued
Array ( [id] => 15831495 [patent_doc_number] => 20200131029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => WATERPROOF MICROPHONE AND ASSOCIATED PACKING TECHNIQUES [patent_app_type] => utility [patent_app_number] => 16/731327 [patent_app_country] => US [patent_app_date] => 2019-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11383 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16731327 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/731327
Waterproof microphone and associated packing techniques Dec 30, 2019 Issued
Array ( [id] => 16888919 [patent_doc_number] => 20210175116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE WITH AIR GAP AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/707177 [patent_app_country] => US [patent_app_date] => 2019-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16707177 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/707177
Semiconductor device structure with air gap and method for forming the same Dec 8, 2019 Issued
Array ( [id] => 17381287 [patent_doc_number] => 11239320 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Classifier circuits with graphene transistors [patent_app_type] => utility [patent_app_number] => 16/706004 [patent_app_country] => US [patent_app_date] => 2019-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 32 [patent_no_of_words] => 5191 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16706004 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/706004
Classifier circuits with graphene transistors Dec 5, 2019 Issued
Array ( [id] => 15687949 [patent_doc_number] => 20200098638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => IR ASSISTED FAN-OUT WAFER LEVEL PACKAGING USING SILICON HANDLER [patent_app_type] => utility [patent_app_number] => 16/693526 [patent_app_country] => US [patent_app_date] => 2019-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6427 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16693526 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/693526
IR assisted fan-out wafer level packaging using silicon handler Nov 24, 2019 Issued
Array ( [id] => 17638138 [patent_doc_number] => 11348872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Hybrid dielectric scheme for varying liner thickness and manganese concentration [patent_app_type] => utility [patent_app_number] => 16/690925 [patent_app_country] => US [patent_app_date] => 2019-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 4198 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16690925 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/690925
Hybrid dielectric scheme for varying liner thickness and manganese concentration Nov 20, 2019 Issued
Array ( [id] => 16020857 [patent_doc_number] => 20200185272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => METHOD OF FORMING CAPPED METALLIZED VIAS [patent_app_type] => utility [patent_app_number] => 16/681330 [patent_app_country] => US [patent_app_date] => 2019-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13548 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16681330 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/681330
Method of forming capped metallized vias Nov 11, 2019 Issued
Array ( [id] => 17359839 [patent_doc_number] => 20220020635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => NANOSCALE RESOLUTION, SPATIALLY-CONTROLLED CONDUCTIVITY MODULATION OF DIELECTRIC MATERIALS USING A FOCUSED ION BEAM [patent_app_type] => utility [patent_app_number] => 17/293276 [patent_app_country] => US [patent_app_date] => 2019-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4828 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17293276 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/293276
NANOSCALE RESOLUTION, SPATIALLY-CONTROLLED CONDUCTIVITY MODULATION OF DIELECTRIC MATERIALS USING A FOCUSED ION BEAM Nov 6, 2019 Pending
Array ( [id] => 15874123 [patent_doc_number] => 20200144465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => LIGHT EMITTING DEVICE [patent_app_type] => utility [patent_app_number] => 16/672691 [patent_app_country] => US [patent_app_date] => 2019-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7641 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16672691 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/672691
Light emitting device including light shielding layer Nov 3, 2019 Issued
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