Dakota M Talbert
Examiner (ID: 4286)
Most Active Art Unit | 2841 |
Art Unit(s) | 2841 |
Total Applications | 46 |
Issued Applications | 8 |
Pending Applications | 36 |
Abandoned Applications | 2 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 16677508
[patent_doc_number] => 20210066274
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-04
[patent_title] => SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/596725
[patent_app_country] => US
[patent_app_date] => 2019-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6559
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16596725
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/596725 | Semiconductor device with exposed input/output pad in recess | Oct 7, 2019 | Issued |
Array
(
[id] => 17623115
[patent_doc_number] => 11342177
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-05-24
[patent_title] => Treatment to control deposition rate
[patent_app_type] => utility
[patent_app_number] => 16/569953
[patent_app_country] => US
[patent_app_date] => 2019-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 27
[patent_no_of_words] => 10175
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16569953
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/569953 | Treatment to control deposition rate | Sep 12, 2019 | Issued |
Array
(
[id] => 15369625
[patent_doc_number] => 20200020577
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-01-16
[patent_title] => VOID-FREE METALLIC INTERCONNECT STRUCTURES WITH SELF-FORMED DIFFUSION BARRIER LAYERS
[patent_app_type] => utility
[patent_app_number] => 16/564518
[patent_app_country] => US
[patent_app_date] => 2019-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7807
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 219
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16564518
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/564518 | Void-free metallic interconnect structures with self-formed diffusion barrier layers | Sep 8, 2019 | Issued |
Array
(
[id] => 17145413
[patent_doc_number] => 20210313426
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-07
[patent_title] => METHOD FOR CONTROLLING CURRENT PATH BY USING ELECTRIC FIELD, AND ELECTRONIC ELEMENT
[patent_app_type] => utility
[patent_app_number] => 17/284106
[patent_app_country] => US
[patent_app_date] => 2019-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4629
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17284106
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/284106 | Method for controlling current path by using electric field, and electronic element | Sep 3, 2019 | Issued |
Array
(
[id] => 15274643
[patent_doc_number] => 20190386056
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-19
[patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD
[patent_app_type] => utility
[patent_app_number] => 16/554347
[patent_app_country] => US
[patent_app_date] => 2019-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9120
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -2
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16554347
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/554347 | Method for bonding and connecting substrates | Aug 27, 2019 | Issued |
Array
(
[id] => 19229612
[patent_doc_number] => 12009255
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-06-11
[patent_title] => Method of manufacturing semiconductor device including laser treatment for contact plug
[patent_app_type] => utility
[patent_app_number] => 17/281966
[patent_app_country] => US
[patent_app_date] => 2019-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2152
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17281966
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/281966 | Method of manufacturing semiconductor device including laser treatment for contact plug | Aug 25, 2019 | Issued |
Array
(
[id] => 15415207
[patent_doc_number] => 20200027926
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-01-23
[patent_title] => CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME
[patent_app_type] => utility
[patent_app_number] => 16/542136
[patent_app_country] => US
[patent_app_date] => 2019-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7967
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16542136
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/542136 | Cross-point memory and methods for fabrication of same | Aug 14, 2019 | Issued |
Array
(
[id] => 15154915
[patent_doc_number] => 20190355935
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-21
[patent_title] => ORGANIC LIGHT EMITTING DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/529030
[patent_app_country] => US
[patent_app_date] => 2019-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9085
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16529030
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/529030 | Organic light emitting display device | Jul 31, 2019 | Issued |
Array
(
[id] => 16920422
[patent_doc_number] => 20210193514
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-24
[patent_title] => ALTERNATIVE INTEGRATION FOR REDISTRIBUTION LAYER PROCESS
[patent_app_type] => utility
[patent_app_number] => 17/263503
[patent_app_country] => US
[patent_app_date] => 2019-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2696
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17263503
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/263503 | Alternative integration for redistribution layer process | Jul 25, 2019 | Issued |
Array
(
[id] => 15123985
[patent_doc_number] => 20190348626
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-14
[patent_title] => ORGANIC LIGHT EMITTING DIODE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/520627
[patent_app_country] => US
[patent_app_date] => 2019-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5654
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16520627
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/520627 | ORGANIC LIGHT EMITTING DIODE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME | Jul 23, 2019 | Abandoned |
Array
(
[id] => 16873504
[patent_doc_number] => 20210166971
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-03
[patent_title] => ZINCATING AND DOPING OF METAL LINER FOR LINER PASSIVATION AND ADHESION IMPROVEMENT
[patent_app_type] => utility
[patent_app_number] => 17/257207
[patent_app_country] => US
[patent_app_date] => 2019-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7850
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17257207
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/257207 | Zincating and doping of metal liner for liner passivation and adhesion improvement | Jun 27, 2019 | Issued |
Array
(
[id] => 17254109
[patent_doc_number] => 11189607
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-11-30
[patent_title] => Transparent micro LED display panel
[patent_app_type] => utility
[patent_app_number] => 16/421848
[patent_app_country] => US
[patent_app_date] => 2019-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2632
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 212
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16421848
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/421848 | Transparent micro LED display panel | May 23, 2019 | Issued |
Array
(
[id] => 16896545
[patent_doc_number] => 11038108
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-15
[patent_title] => Step height mitigation in resistive random access memory structures
[patent_app_type] => utility
[patent_app_number] => 16/422207
[patent_app_country] => US
[patent_app_date] => 2019-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 7872
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16422207
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/422207 | Step height mitigation in resistive random access memory structures | May 23, 2019 | Issued |
Array
(
[id] => 16973620
[patent_doc_number] => 11069600
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-07-20
[patent_title] => Semiconductor package with space efficient lead and die pad design
[patent_app_type] => utility
[patent_app_number] => 16/422163
[patent_app_country] => US
[patent_app_date] => 2019-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 6
[patent_no_of_words] => 6156
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16422163
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/422163 | Semiconductor package with space efficient lead and die pad design | May 23, 2019 | Issued |
Array
(
[id] => 15657327
[patent_doc_number] => 20200091194
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-19
[patent_title] => DISPLAY SUBSTRATE, METHOD FOR PREPARING THE SAME, AND DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/422074
[patent_app_country] => US
[patent_app_date] => 2019-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4010
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16422074
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/422074 | DISPLAY SUBSTRATE, METHOD FOR PREPARING THE SAME, AND DISPLAY DEVICE | May 23, 2019 | Abandoned |
Array
(
[id] => 15218121
[patent_doc_number] => 20190371747
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-05
[patent_title] => LAUNCH STRUCTURES FOR RADIO FREQUENCY INTEGRATED DEVICE PACKAGES
[patent_app_type] => utility
[patent_app_number] => 16/421221
[patent_app_country] => US
[patent_app_date] => 2019-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9232
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16421221
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/421221 | Launch structures for radio frequency integrated device packages | May 22, 2019 | Issued |
Array
(
[id] => 17166324
[patent_doc_number] => 11152437
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-10-19
[patent_title] => Display apparatus having self-aligned structures and method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 16/420930
[patent_app_country] => US
[patent_app_date] => 2019-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 18
[patent_no_of_words] => 5639
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16420930
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/420930 | Display apparatus having self-aligned structures and method of manufacturing the same | May 22, 2019 | Issued |
Array
(
[id] => 17166197
[patent_doc_number] => 11152309
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-10-19
[patent_title] => Semiconductor package, method of fabricating semiconductor package, and method of fabricating redistribution structure
[patent_app_type] => utility
[patent_app_number] => 16/411586
[patent_app_country] => US
[patent_app_date] => 2019-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 22
[patent_no_of_words] => 7492
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16411586
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/411586 | Semiconductor package, method of fabricating semiconductor package, and method of fabricating redistribution structure | May 13, 2019 | Issued |
Array
(
[id] => 15547939
[patent_doc_number] => 10573762
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-02-25
[patent_title] => Vertical gallium nitride Schottky diode
[patent_app_type] => utility
[patent_app_number] => 16/397720
[patent_app_country] => US
[patent_app_date] => 2019-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 34
[patent_no_of_words] => 8127
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16397720
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/397720 | Vertical gallium nitride Schottky diode | Apr 28, 2019 | Issued |
Array
(
[id] => 14691411
[patent_doc_number] => 20190244821
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-08
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/385161
[patent_app_country] => US
[patent_app_date] => 2019-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8137
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16385161
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/385161 | Method for manufacturing gate insulator for HEMT | Apr 15, 2019 | Issued |