Dakota M Talbert
Examiner (ID: 4286)
Most Active Art Unit | 2841 |
Art Unit(s) | 2841 |
Total Applications | 46 |
Issued Applications | 8 |
Pending Applications | 36 |
Abandoned Applications | 2 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 16379301
[patent_doc_number] => 20200328144
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-15
[patent_title] => SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/382229
[patent_app_country] => US
[patent_app_date] => 2019-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7431
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16382229
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/382229 | Semiconductor package with conductive via in encapsulation connecting to conductive element | Apr 11, 2019 | Issued |
Array
(
[id] => 17326486
[patent_doc_number] => 11217511
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-01-04
[patent_title] => Quad package with conductive clips connected to terminals at upper surface of semiconductor die
[patent_app_type] => utility
[patent_app_number] => 16/379405
[patent_app_country] => US
[patent_app_date] => 2019-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 23
[patent_no_of_words] => 5933
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16379405
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/379405 | Quad package with conductive clips connected to terminals at upper surface of semiconductor die | Apr 8, 2019 | Issued |
Array
(
[id] => 16364525
[patent_doc_number] => 20200321276
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-08
[patent_title] => Chip to Chip Interconnect in Encapsulant of Molded Semiconductor Package
[patent_app_type] => utility
[patent_app_number] => 16/375479
[patent_app_country] => US
[patent_app_date] => 2019-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5093
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16375479
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/375479 | Chip to chip interconnect in encapsulant of molded semiconductor package | Apr 3, 2019 | Issued |
Array
(
[id] => 15442835
[patent_doc_number] => 20200035601
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-01-30
[patent_title] => SEMICONDUCTOR DEVICE HAVING SYMMETRIC CONDUCTIVE INTERCONNECTION PATTERNS
[patent_app_type] => utility
[patent_app_number] => 16/358661
[patent_app_country] => US
[patent_app_date] => 2019-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4876
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -37
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358661
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/358661 | SEMICONDUCTOR DEVICE HAVING SYMMETRIC CONDUCTIVE INTERCONNECTION PATTERNS | Mar 18, 2019 | Abandoned |
Array
(
[id] => 16332373
[patent_doc_number] => 20200303339
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-24
[patent_title] => LEAD-FREE COLUMN INTERCONNECT
[patent_app_type] => utility
[patent_app_number] => 16/358658
[patent_app_country] => US
[patent_app_date] => 2019-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4403
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358658
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/358658 | Lead-free column interconnect | Mar 18, 2019 | Issued |
Array
(
[id] => 16301052
[patent_doc_number] => 20200286775
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-10
[patent_title] => INTERCONNECT STRUCTURE AND METHOD FOR PREPARING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/291376
[patent_app_country] => US
[patent_app_date] => 2019-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6968
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291376
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/291376 | INTERCONNECT STRUCTURE AND METHOD FOR PREPARING THE SAME | Mar 3, 2019 | Abandoned |
Array
(
[id] => 16301152
[patent_doc_number] => 20200286875
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-10
[patent_title] => THREE-DIMENSIONAL DEVICE WITH BONDED STRUCTURES INCLUDING A SUPPORT DIE AND METHODS OF MAKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/291504
[patent_app_country] => US
[patent_app_date] => 2019-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 41770
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 284
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291504
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/291504 | Three-dimensional device with bonded structures including a support die and methods of making the same | Mar 3, 2019 | Issued |
Array
(
[id] => 14843049
[patent_doc_number] => 20190279925
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-09-12
[patent_title] => SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MAKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/291065
[patent_app_country] => US
[patent_app_date] => 2019-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6334
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291065
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/291065 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MAKING THE SAME | Mar 3, 2019 | Abandoned |
Array
(
[id] => 14350805
[patent_doc_number] => 20190157375
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-23
[patent_title] => DISPLAY PANEL AND DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/255821
[patent_app_country] => US
[patent_app_date] => 2019-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4808
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16255821
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/255821 | Display panel and display device | Jan 23, 2019 | Issued |
Array
(
[id] => 14753097
[patent_doc_number] => 20190259722
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-22
[patent_title] => COPPER PILLARS HAVING IMPROVED INTEGRITY AND METHODS OF MAKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/255124
[patent_app_country] => US
[patent_app_date] => 2019-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9031
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16255124
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/255124 | COPPER PILLARS HAVING IMPROVED INTEGRITY AND METHODS OF MAKING THE SAME | Jan 22, 2019 | Abandoned |
Array
(
[id] => 16001095
[patent_doc_number] => 20200176418
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-04
[patent_title] => DUAL-DIE MEMORY PACKAGE
[patent_app_type] => utility
[patent_app_number] => 16/254599
[patent_app_country] => US
[patent_app_date] => 2019-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3720
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16254599
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/254599 | DUAL-DIE MEMORY PACKAGE | Jan 22, 2019 | Abandoned |
Array
(
[id] => 15889805
[patent_doc_number] => 10651259
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-05-12
[patent_title] => Display device with transparent capacitor
[patent_app_type] => utility
[patent_app_number] => 16/251747
[patent_app_country] => US
[patent_app_date] => 2019-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 6511
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16251747
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/251747 | Display device with transparent capacitor | Jan 17, 2019 | Issued |
Array
(
[id] => 16928320
[patent_doc_number] => 11049811
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-29
[patent_title] => Forming interlayer dielectric material by spin-on metal oxide deposition
[patent_app_type] => utility
[patent_app_number] => 16/232921
[patent_app_country] => US
[patent_app_date] => 2018-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 5171
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16232921
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/232921 | Forming interlayer dielectric material by spin-on metal oxide deposition | Dec 25, 2018 | Issued |
Array
(
[id] => 15286469
[patent_doc_number] => 10515904
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-12-24
[patent_title] => Method for forming chip package structure
[patent_app_type] => utility
[patent_app_number] => 16/229021
[patent_app_country] => US
[patent_app_date] => 2018-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 20
[patent_no_of_words] => 6405
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16229021
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/229021 | Method for forming chip package structure | Dec 20, 2018 | Issued |
Array
(
[id] => 15154821
[patent_doc_number] => 20190355888
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-21
[patent_title] => LIGHT EMITTING CHIP AND ASSOCIATED PACKAGE STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 16/221891
[patent_app_country] => US
[patent_app_date] => 2018-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5573
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16221891
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/221891 | LIGHT EMITTING CHIP AND ASSOCIATED PACKAGE STRUCTURE | Dec 16, 2018 | Abandoned |
Array
(
[id] => 16080871
[patent_doc_number] => 20200194422
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-18
[patent_title] => DIELECTRIC SPACED DIODE
[patent_app_type] => utility
[patent_app_number] => 16/220793
[patent_app_country] => US
[patent_app_date] => 2018-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9331
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16220793
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/220793 | Dielectric spaced diode | Dec 13, 2018 | Issued |
Array
(
[id] => 16835248
[patent_doc_number] => 11011508
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-05-18
[patent_title] => Dielectric spaced diode
[patent_app_type] => utility
[patent_app_number] => 16/220881
[patent_app_country] => US
[patent_app_date] => 2018-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 27
[patent_no_of_words] => 6602
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16220881
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/220881 | Dielectric spaced diode | Dec 13, 2018 | Issued |
Array
(
[id] => 14938513
[patent_doc_number] => 20190304895
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-03
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/181739
[patent_app_country] => US
[patent_app_date] => 2018-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6657
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16181739
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/181739 | Semiconductor device with air gaps in interlayer insulating layer and method of manufacturing the same | Nov 5, 2018 | Issued |
Array
(
[id] => 14285267
[patent_doc_number] => 20190139918
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-09
[patent_title] => SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
[patent_app_type] => utility
[patent_app_number] => 16/181383
[patent_app_country] => US
[patent_app_date] => 2018-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4427
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16181383
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/181383 | Semiconductor device bonding area including fused solder film and manufacturing method | Nov 5, 2018 | Issued |
Array
(
[id] => 16894552
[patent_doc_number] => 11036100
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-15
[patent_title] => Display device
[patent_app_type] => utility
[patent_app_number] => 16/181380
[patent_app_country] => US
[patent_app_date] => 2018-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 16
[patent_no_of_words] => 6802
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16181380
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/181380 | Display device | Nov 5, 2018 | Issued |