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Dakota M Talbert

Examiner (ID: 4286)

Most Active Art Unit
2841
Art Unit(s)
2841
Total Applications
46
Issued Applications
8
Pending Applications
36
Abandoned Applications
2

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15286265 [patent_doc_number] => 10515802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Techniques for forming low stress mask using implantation [patent_app_type] => utility [patent_app_number] => 16/030311 [patent_app_country] => US [patent_app_date] => 2018-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 5698 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16030311 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/030311
Techniques for forming low stress mask using implantation Jul 8, 2018 Issued
Array ( [id] => 13543537 [patent_doc_number] => 20180323315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => TERMINATION STRUCTURE FOR GALLIUM NITRIDE SCHOTTKY DIODE INCLUDING JUNCTION BARRIAR DIODES [patent_app_type] => utility [patent_app_number] => 16/019085 [patent_app_country] => US [patent_app_date] => 2018-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7313 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16019085 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/019085
Termination structure for gallium nitride Schottky diode including junction barriar diodes Jun 25, 2018 Issued
Array ( [id] => 13571141 [patent_doc_number] => 20180337118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => Interconnection Substrates for Interconnection Between Circuit Modules, and Methods of Manufacture [patent_app_type] => utility [patent_app_number] => 16/017010 [patent_app_country] => US [patent_app_date] => 2018-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5608 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16017010 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/017010
Interconnection substrates for interconnection between circuit modules, and methods of manufacture Jun 24, 2018 Issued
Array ( [id] => 13485573 [patent_doc_number] => 20180294329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => METAL RESISTORS HAVING NITRIDIZED DIELECTRIC SURFACE LAYERS AND NITRIDIZED METAL SURFACE LAYERS [patent_app_type] => utility [patent_app_number] => 16/004103 [patent_app_country] => US [patent_app_date] => 2018-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9200 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16004103 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/004103
Metal resistors having nitridized dielectric surface layers and nitridized metal surface layers Jun 7, 2018 Issued
Array ( [id] => 13435411 [patent_doc_number] => 20180269248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 15/987278 [patent_app_country] => US [patent_app_date] => 2018-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15987278 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/987278
Semiconductor device with multiple substrates electrically connected through an insulating film May 22, 2018 Issued
Array ( [id] => 13364197 [patent_doc_number] => 20180233638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => LIGHT EMITTING DEVICE [patent_app_type] => utility [patent_app_number] => 15/953082 [patent_app_country] => US [patent_app_date] => 2018-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7023 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15953082 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/953082
Method of manufacturing light emitting device with light-transmissive members Apr 12, 2018 Issued
Array ( [id] => 18688512 [patent_doc_number] => 11784258 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Thin film transistor with insulating portion between source/drian electrode and gate insulating layer, and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/309786 [patent_app_country] => US [patent_app_date] => 2018-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 5600 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16309786 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/309786
Thin film transistor with insulating portion between source/drian electrode and gate insulating layer, and manufacturing method thereof Apr 3, 2018 Issued
Array ( [id] => 14125677 [patent_doc_number] => 10249703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Metal resistors having nitridized metal surface layers with different nitrogen content [patent_app_type] => utility [patent_app_number] => 15/935942 [patent_app_country] => US [patent_app_date] => 2018-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7261 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15935942 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/935942
Metal resistors having nitridized metal surface layers with different nitrogen content Mar 25, 2018 Issued
Array ( [id] => 12918295 [patent_doc_number] => 20180197941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => METAL RESISTORS HAVING VARYING RESISTIVITY [patent_app_type] => utility [patent_app_number] => 15/914106 [patent_app_country] => US [patent_app_date] => 2018-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7112 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15914106 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/914106
Metal resistors having varying resistivity Mar 6, 2018 Issued
Array ( [id] => 15315385 [patent_doc_number] => 10522406 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => IR assisted fan-out wafer level packaging using silicon handler [patent_app_type] => utility [patent_app_number] => 15/903973 [patent_app_country] => US [patent_app_date] => 2018-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 6426 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15903973 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/903973
IR assisted fan-out wafer level packaging using silicon handler Feb 22, 2018 Issued
Array ( [id] => 13174293 [patent_doc_number] => 10103271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-16 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/879023 [patent_app_country] => US [patent_app_date] => 2018-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 80 [patent_no_of_words] => 34509 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15879023 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/879023
Semiconductor device Jan 23, 2018 Issued
Array ( [id] => 13111813 [patent_doc_number] => 10074564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-11 [patent_title] => Self-aligned middle of the line (MOL) contacts [patent_app_type] => utility [patent_app_number] => 15/878486 [patent_app_country] => US [patent_app_date] => 2018-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 40 [patent_no_of_words] => 10671 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15878486 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/878486
Self-aligned middle of the line (MOL) contacts Jan 23, 2018 Issued
Array ( [id] => 14955443 [patent_doc_number] => 10439001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-08 [patent_title] => Cross-point memory and methods for fabrication of same [patent_app_type] => utility [patent_app_number] => 15/858811 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 7918 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15858811 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/858811
Cross-point memory and methods for fabrication of same Dec 28, 2017 Issued
Array ( [id] => 14476013 [patent_doc_number] => 20190189655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => METHOD FOR MAKING CMOS IMAGE SENSOR INCLUDING STACKED SEMICONDUCTOR CHIPS AND READOUT CIRCUITRY INCLUDING A SUPERLATTICE [patent_app_type] => utility [patent_app_number] => 15/842993 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15842993 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/842993
Method for making CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice Dec 14, 2017 Issued
Array ( [id] => 15376079 [patent_doc_number] => 10529768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => Method for making CMOS image sensor including pixels with read circuitry having a superlattice [patent_app_type] => utility [patent_app_number] => 15/843113 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 6039 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15843113 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/843113
Method for making CMOS image sensor including pixels with read circuitry having a superlattice Dec 14, 2017 Issued
Array ( [id] => 14476017 [patent_doc_number] => 20190189657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => METHOD FOR MAKING CMOS IMAGE SENSOR INCLUDING STACKED SEMICONDUCTOR CHIPS AND IMAGE PROCESSING CIRCUITRY INCLUDING A SUPERLATTICE [patent_app_type] => utility [patent_app_number] => 15/842981 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6072 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15842981 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/842981
Method for making CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice Dec 14, 2017 Issued
Array ( [id] => 14617071 [patent_doc_number] => 10361243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Method for making CMOS image sensor including superlattice to enhance infrared light absorption [patent_app_type] => utility [patent_app_number] => 15/843013 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4842 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15843013 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/843013
Method for making CMOS image sensor including superlattice to enhance infrared light absorption Dec 14, 2017 Issued
Array ( [id] => 13951079 [patent_doc_number] => 10211321 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => Stress retention in fins of fin field-effect transistors [patent_app_type] => utility [patent_app_number] => 15/835906 [patent_app_country] => US [patent_app_date] => 2017-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 6065 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15835906 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/835906
Stress retention in fins of fin field-effect transistors Dec 7, 2017 Issued
Array ( [id] => 12596163 [patent_doc_number] => 20180090551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 15/830041 [patent_app_country] => US [patent_app_date] => 2017-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6471 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15830041 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/830041
Display device including capacitor having transparency Dec 3, 2017 Issued
Array ( [id] => 14859511 [patent_doc_number] => 10418492 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Semiconductor device with curved active layer [patent_app_type] => utility [patent_app_number] => 15/798480 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 83 [patent_no_of_words] => 36490 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15798480 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/798480
Semiconductor device with curved active layer Oct 30, 2017 Issued
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