
Dale M. Shaw
Examiner (ID: 10068)
| Most Active Art Unit | 2301 |
| Art Unit(s) | 2317, 2311, 2302, 2301 |
| Total Applications | 433 |
| Issued Applications | 390 |
| Pending Applications | 0 |
| Abandoned Applications | 43 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2776254
[patent_doc_number] => 05036482
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-30
[patent_title] => 'Method and circuitry for digital system multiplication'
[patent_app_type] => 1
[patent_app_number] => 7/335125
[patent_app_country] => US
[patent_app_date] => 1989-04-07
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[pdf_file] => patents/05/036/05036482.pdf
[firstpage_image] =>[orig_patent_app_number] => 335125
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/335125 | Method and circuitry for digital system multiplication | Apr 6, 1989 | Issued |
Array
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[patent_doc_number] => 04974183
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-11-27
[patent_title] => 'Computer keyboard with thumb-actuated edit keys'
[patent_app_type] => 1
[patent_app_number] => 7/333216
[patent_app_country] => US
[patent_app_date] => 1989-04-05
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/333216 | Computer keyboard with thumb-actuated edit keys | Apr 4, 1989 | Issued |
Array
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[patent_issue_date] => 1992-01-14
[patent_title] => 'Correction for Compton scattering by analysis of energy spectra'
[patent_app_type] => 1
[patent_app_number] => 7/331993
[patent_app_country] => US
[patent_app_date] => 1989-03-31
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[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/05/081/05081581.pdf
[firstpage_image] =>[orig_patent_app_number] => 331993
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/331993 | Correction for Compton scattering by analysis of energy spectra | Mar 30, 1989 | Issued |
Array
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[patent_issue_date] => 1992-06-16
[patent_title] => 'Floating point processor with high speed rounding circuit'
[patent_app_type] => 1
[patent_app_number] => 7/327656
[patent_app_country] => US
[patent_app_date] => 1989-03-23
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[firstpage_image] =>[orig_patent_app_number] => 327656
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/327656 | Floating point processor with high speed rounding circuit | Mar 22, 1989 | Issued |
Array
(
[id] => 2640626
[patent_doc_number] => 04977534
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[patent_kind] => NA
[patent_issue_date] => 1990-12-11
[patent_title] => 'Operation circuit based on floating-point representation with selective bypass for increasing processing speed'
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[patent_app_number] => 7/320496
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[patent_app_date] => 1989-03-08
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[pdf_file] => patents/04/977/04977534.pdf
[firstpage_image] =>[orig_patent_app_number] => 320496
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/320496 | Operation circuit based on floating-point representation with selective bypass for increasing processing speed | Mar 7, 1989 | Issued |
| 07/320867 | METHOD AND APPARATUS FOR FAST LOGARITHMIC ADDITION AND SUBTRACTION | Mar 6, 1989 | Abandoned |
Array
(
[id] => 2655369
[patent_doc_number] => 04980849
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[patent_issue_date] => 1990-12-25
[patent_title] => 'Method and apparatus for autoregressive model simulation'
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[patent_app_date] => 1989-02-28
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[firstpage_image] =>[orig_patent_app_number] => 316616
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/316616 | Method and apparatus for autoregressive model simulation | Feb 27, 1989 | Issued |
| 07/316568 | METHOD OF INTERPOLATING PIXEL VALUES | Feb 26, 1989 | Abandoned |
Array
(
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[patent_issue_date] => 1991-01-01
[patent_title] => 'Multiple-valued current mode adder implemented by transistor having negative transconductance'
[patent_app_type] => 1
[patent_app_number] => 7/313485
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[patent_app_date] => 1989-02-22
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/313485 | Multiple-valued current mode adder implemented by transistor having negative transconductance | Feb 21, 1989 | Issued |
Array
(
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[patent_issue_date] => 1991-02-12
[patent_title] => 'Division method and apparatus including use of a Z--Z plot to select acceptable quotient bits'
[patent_app_type] => 1
[patent_app_number] => 7/312085
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[patent_app_date] => 1989-02-17
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/312085 | Division method and apparatus including use of a Z--Z plot to select acceptable quotient bits | Feb 16, 1989 | Issued |
Array
(
[id] => 2742115
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[patent_issue_date] => 1991-03-05
[patent_title] => 'Method and apparatus for determining the greatest value of a binary number and for minimizing any uncertainty associated with the determination'
[patent_app_type] => 1
[patent_app_number] => 7/312674
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/312674 | Method and apparatus for determining the greatest value of a binary number and for minimizing any uncertainty associated with the determination | Feb 15, 1989 | Issued |
Array
(
[id] => 2682479
[patent_doc_number] => 05027308
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[patent_issue_date] => 1991-06-25
[patent_title] => 'Circuit for adding/subtracting two floating point operands'
[patent_app_type] => 1
[patent_app_number] => 7/311296
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[firstpage_image] =>[orig_patent_app_number] => 311296
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/311296 | Circuit for adding/subtracting two floating point operands | Feb 13, 1989 | Issued |
Array
(
[id] => 2753814
[patent_doc_number] => 04987557
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[patent_issue_date] => 1991-01-22
[patent_title] => 'System for calculation of sum of products by repetitive input of data'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/314055 | System for calculation of sum of products by repetitive input of data | Feb 8, 1989 | Issued |
Array
(
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[patent_title] => 'Absolute value calculating circuit having a single adder'
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Array
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[id] => 2640348
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[patent_issue_date] => 1990-09-18
[patent_title] => 'CMOS parallel-serial multiplication circuit and multiplying and adding stages thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/307125 | CMOS parallel-serial multiplication circuit and multiplying and adding stages thereof | Feb 5, 1989 | Issued |
Array
(
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[patent_title] => 'High speed digital signal processor for signed digit numbers'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/302346 | High speed digital signal processor for signed digit numbers | Jan 26, 1989 | Issued |
Array
(
[id] => 2721859
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Array
(
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[patent_title] => 'Floating point unit for calculating A=XY+Z having simultaneous multiply and add'
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Array
(
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Array
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