Search

Dale M. Shaw

Examiner (ID: 10068)

Most Active Art Unit
2301
Art Unit(s)
2317, 2311, 2302, 2301
Total Applications
433
Issued Applications
390
Pending Applications
0
Abandoned Applications
43

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2776254 [patent_doc_number] => 05036482 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-30 [patent_title] => 'Method and circuitry for digital system multiplication' [patent_app_type] => 1 [patent_app_number] => 7/335125 [patent_app_country] => US [patent_app_date] => 1989-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 12733 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/036/05036482.pdf [firstpage_image] =>[orig_patent_app_number] => 335125 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/335125
Method and circuitry for digital system multiplication Apr 6, 1989 Issued
Array ( [id] => 2589055 [patent_doc_number] => 04974183 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-11-27 [patent_title] => 'Computer keyboard with thumb-actuated edit keys' [patent_app_type] => 1 [patent_app_number] => 7/333216 [patent_app_country] => US [patent_app_date] => 1989-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3219 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/974/04974183.pdf [firstpage_image] =>[orig_patent_app_number] => 333216 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/333216
Computer keyboard with thumb-actuated edit keys Apr 4, 1989 Issued
Array ( [id] => 2826549 [patent_doc_number] => 05081581 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-01-14 [patent_title] => 'Correction for Compton scattering by analysis of energy spectra' [patent_app_type] => 1 [patent_app_number] => 7/331993 [patent_app_country] => US [patent_app_date] => 1989-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3588 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/081/05081581.pdf [firstpage_image] =>[orig_patent_app_number] => 331993 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/331993
Correction for Compton scattering by analysis of energy spectra Mar 30, 1989 Issued
Array ( [id] => 2824053 [patent_doc_number] => 05122981 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-16 [patent_title] => 'Floating point processor with high speed rounding circuit' [patent_app_type] => 1 [patent_app_number] => 7/327656 [patent_app_country] => US [patent_app_date] => 1989-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 9936 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/122/05122981.pdf [firstpage_image] =>[orig_patent_app_number] => 327656 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/327656
Floating point processor with high speed rounding circuit Mar 22, 1989 Issued
Array ( [id] => 2640626 [patent_doc_number] => 04977534 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-12-11 [patent_title] => 'Operation circuit based on floating-point representation with selective bypass for increasing processing speed' [patent_app_type] => 1 [patent_app_number] => 7/320496 [patent_app_country] => US [patent_app_date] => 1989-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4205 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 482 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/977/04977534.pdf [firstpage_image] =>[orig_patent_app_number] => 320496 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/320496
Operation circuit based on floating-point representation with selective bypass for increasing processing speed Mar 7, 1989 Issued
07/320867 METHOD AND APPARATUS FOR FAST LOGARITHMIC ADDITION AND SUBTRACTION Mar 6, 1989 Abandoned
Array ( [id] => 2655369 [patent_doc_number] => 04980849 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-12-25 [patent_title] => 'Method and apparatus for autoregressive model simulation' [patent_app_type] => 1 [patent_app_number] => 7/316616 [patent_app_country] => US [patent_app_date] => 1989-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4128 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/980/04980849.pdf [firstpage_image] =>[orig_patent_app_number] => 316616 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/316616
Method and apparatus for autoregressive model simulation Feb 27, 1989 Issued
07/316568 METHOD OF INTERPOLATING PIXEL VALUES Feb 26, 1989 Abandoned
Array ( [id] => 2716712 [patent_doc_number] => 04982356 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-01 [patent_title] => 'Multiple-valued current mode adder implemented by transistor having negative transconductance' [patent_app_type] => 1 [patent_app_number] => 7/313485 [patent_app_country] => US [patent_app_date] => 1989-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4460 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/982/04982356.pdf [firstpage_image] =>[orig_patent_app_number] => 313485 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/313485
Multiple-valued current mode adder implemented by transistor having negative transconductance Feb 21, 1989 Issued
Array ( [id] => 2715724 [patent_doc_number] => 04992968 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-12 [patent_title] => 'Division method and apparatus including use of a Z--Z plot to select acceptable quotient bits' [patent_app_type] => 1 [patent_app_number] => 7/312085 [patent_app_country] => US [patent_app_date] => 1989-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 11984 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/992/04992968.pdf [firstpage_image] =>[orig_patent_app_number] => 312085 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/312085
Division method and apparatus including use of a Z--Z plot to select acceptable quotient bits Feb 16, 1989 Issued
Array ( [id] => 2742115 [patent_doc_number] => 04998219 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-03-05 [patent_title] => 'Method and apparatus for determining the greatest value of a binary number and for minimizing any uncertainty associated with the determination' [patent_app_type] => 1 [patent_app_number] => 7/312674 [patent_app_country] => US [patent_app_date] => 1989-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6267 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/998/04998219.pdf [firstpage_image] =>[orig_patent_app_number] => 312674 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/312674
Method and apparatus for determining the greatest value of a binary number and for minimizing any uncertainty associated with the determination Feb 15, 1989 Issued
Array ( [id] => 2682479 [patent_doc_number] => 05027308 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-25 [patent_title] => 'Circuit for adding/subtracting two floating point operands' [patent_app_type] => 1 [patent_app_number] => 7/311296 [patent_app_country] => US [patent_app_date] => 1989-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 11119 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/027/05027308.pdf [firstpage_image] =>[orig_patent_app_number] => 311296 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/311296
Circuit for adding/subtracting two floating point operands Feb 13, 1989 Issued
Array ( [id] => 2753814 [patent_doc_number] => 04987557 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-22 [patent_title] => 'System for calculation of sum of products by repetitive input of data' [patent_app_type] => 1 [patent_app_number] => 7/314055 [patent_app_country] => US [patent_app_date] => 1989-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4009 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/987/04987557.pdf [firstpage_image] =>[orig_patent_app_number] => 314055 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/314055
System for calculation of sum of products by repetitive input of data Feb 8, 1989 Issued
Array ( [id] => 2643520 [patent_doc_number] => 04953115 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-08-28 [patent_title] => 'Absolute value calculating circuit having a single adder' [patent_app_type] => 1 [patent_app_number] => 7/308296 [patent_app_country] => US [patent_app_date] => 1989-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2086 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/953/04953115.pdf [firstpage_image] =>[orig_patent_app_number] => 308296 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/308296
Absolute value calculating circuit having a single adder Feb 8, 1989 Issued
Array ( [id] => 2640348 [patent_doc_number] => 04958313 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-09-18 [patent_title] => 'CMOS parallel-serial multiplication circuit and multiplying and adding stages thereof' [patent_app_type] => 1 [patent_app_number] => 7/307125 [patent_app_country] => US [patent_app_date] => 1989-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6721 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/958/04958313.pdf [firstpage_image] =>[orig_patent_app_number] => 307125 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/307125
CMOS parallel-serial multiplication circuit and multiplying and adding stages thereof Feb 5, 1989 Issued
Array ( [id] => 2779071 [patent_doc_number] => 04985861 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-15 [patent_title] => 'High speed digital signal processor for signed digit numbers' [patent_app_type] => 1 [patent_app_number] => 7/302346 [patent_app_country] => US [patent_app_date] => 1989-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3920 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/985/04985861.pdf [firstpage_image] =>[orig_patent_app_number] => 302346 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/302346
High speed digital signal processor for signed digit numbers Jan 26, 1989 Issued
Array ( [id] => 2721859 [patent_doc_number] => 05010507 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-23 [patent_title] => 'Sampled digital filter system' [patent_app_type] => 1 [patent_app_number] => 7/301406 [patent_app_country] => US [patent_app_date] => 1989-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1626 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/010/05010507.pdf [firstpage_image] =>[orig_patent_app_number] => 301406 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/301406
Sampled digital filter system Jan 24, 1989 Issued
Array ( [id] => 2626604 [patent_doc_number] => 04969118 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-11-06 [patent_title] => 'Floating point unit for calculating A=XY+Z having simultaneous multiply and add' [patent_app_type] => 1 [patent_app_number] => 7/297016 [patent_app_country] => US [patent_app_date] => 1989-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4461 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/969/04969118.pdf [firstpage_image] =>[orig_patent_app_number] => 297016 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/297016
Floating point unit for calculating A=XY+Z having simultaneous multiply and add Jan 12, 1989 Issued
Array ( [id] => 2743670 [patent_doc_number] => 05051942 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-24 [patent_title] => 'Method and apparatus for calculating filter factors' [patent_app_type] => 1 [patent_app_number] => 7/285606 [patent_app_country] => US [patent_app_date] => 1988-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5286 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/051/05051942.pdf [firstpage_image] =>[orig_patent_app_number] => 285606 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/285606
Method and apparatus for calculating filter factors Dec 14, 1988 Issued
Array ( [id] => 2705880 [patent_doc_number] => 04991132 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-05 [patent_title] => 'Apparatus for executing division by high-speed convergence processing' [patent_app_type] => 1 [patent_app_number] => 7/285605 [patent_app_country] => US [patent_app_date] => 1988-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7247 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/991/04991132.pdf [firstpage_image] =>[orig_patent_app_number] => 285605 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/285605
Apparatus for executing division by high-speed convergence processing Dec 14, 1988 Issued
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