Search

Dan Davidson

Examiner (ID: 17565)

Most Active Art Unit
2651
Art Unit(s)
2651, 2753, 2627
Total Applications
393
Issued Applications
356
Pending Applications
11
Abandoned Applications
26

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5926428 [patent_doc_number] => 20020116577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Cache hints for computer file access' [patent_app_type] => new [patent_app_number] => 09/785421 [patent_app_country] => US [patent_app_date] => 2001-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5479 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20020116577.pdf [firstpage_image] =>[orig_patent_app_number] => 09785421 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/785421
Cache hints for computer file access Feb 19, 2001 Issued
Array ( [id] => 6245366 [patent_doc_number] => 20020046321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'Disk controller and method of controlling the cache' [patent_app_type] => new [patent_app_number] => 09/785477 [patent_app_country] => US [patent_app_date] => 2001-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7686 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20020046321.pdf [firstpage_image] =>[orig_patent_app_number] => 09785477 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/785477
Disk controller and method of controlling the cache Feb 19, 2001 Issued
Array ( [id] => 5926432 [patent_doc_number] => 20020116579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Cyclically sequential memory prefetch' [patent_app_type] => new [patent_app_number] => 09/788692 [patent_app_country] => US [patent_app_date] => 2001-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4200 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20020116579.pdf [firstpage_image] =>[orig_patent_app_number] => 09788692 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/788692
Cyclically sequential memory prefetch Feb 19, 2001 Issued
Array ( [id] => 1329135 [patent_doc_number] => 06606690 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-12 [patent_title] => 'System and method for accessing a storage area network as network attached storage' [patent_app_type] => B2 [patent_app_number] => 09/785473 [patent_app_country] => US [patent_app_date] => 2001-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 32 [patent_no_of_words] => 24557 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/606/06606690.pdf [firstpage_image] =>[orig_patent_app_number] => 09785473 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/785473
System and method for accessing a storage area network as network attached storage Feb 19, 2001 Issued
Array ( [id] => 7095081 [patent_doc_number] => 20010034821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-25 [patent_title] => 'Program-downloadable data processing system and method for accessing memory by using a unified memory space therein' [patent_app_type] => new [patent_app_number] => 09/779557 [patent_app_country] => US [patent_app_date] => 2001-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6688 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20010034821.pdf [firstpage_image] =>[orig_patent_app_number] => 09779557 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/779557
Program-downloadable data processing system and method for accessing memory by using a unified memory space therein Feb 8, 2001 Issued
Array ( [id] => 1325130 [patent_doc_number] => 06615313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-02 [patent_title] => 'Disk input/output control device maintaining write data in multiple cache memory modules and method and medium thereof' [patent_app_type] => B2 [patent_app_number] => 09/779845 [patent_app_country] => US [patent_app_date] => 2001-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 5545 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/615/06615313.pdf [firstpage_image] =>[orig_patent_app_number] => 09779845 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/779845
Disk input/output control device maintaining write data in multiple cache memory modules and method and medium thereof Feb 8, 2001 Issued
Array ( [id] => 1347750 [patent_doc_number] => 06598119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-22 [patent_title] => 'Database management system with a multiple-level cache arrangement' [patent_app_type] => B2 [patent_app_number] => 09/780633 [patent_app_country] => US [patent_app_date] => 2001-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3785 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/598/06598119.pdf [firstpage_image] =>[orig_patent_app_number] => 09780633 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/780633
Database management system with a multiple-level cache arrangement Feb 8, 2001 Issued
Array ( [id] => 1431449 [patent_doc_number] => 06519689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-11 [patent_title] => 'Method and system for processing pipelined memory commands' [patent_app_type] => B2 [patent_app_number] => 09/764567 [patent_app_country] => US [patent_app_date] => 2001-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10150 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/519/06519689.pdf [firstpage_image] =>[orig_patent_app_number] => 09764567 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/764567
Method and system for processing pipelined memory commands Jan 15, 2001 Issued
Array ( [id] => 1434042 [patent_doc_number] => 06341332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-01-22 [patent_title] => 'Disk array controller with connection path formed on connection request queue basis' [patent_app_type] => B2 [patent_app_number] => 09/756748 [patent_app_country] => US [patent_app_date] => 2001-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 5752 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/341/06341332.pdf [firstpage_image] =>[orig_patent_app_number] => 09756748 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/756748
Disk array controller with connection path formed on connection request queue basis Jan 9, 2001 Issued
Array ( [id] => 1443901 [patent_doc_number] => 06336165 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-01-01 [patent_title] => 'Disk array controller with connection path formed on connection request queue basis' [patent_app_type] => B2 [patent_app_number] => 09/756798 [patent_app_country] => US [patent_app_date] => 2001-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 5808 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/336/06336165.pdf [firstpage_image] =>[orig_patent_app_number] => 09756798 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/756798
Disk array controller with connection path formed on connection request queue basis Jan 9, 2001 Issued
Array ( [id] => 6078381 [patent_doc_number] => 20020080652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Enhanced special programming mode' [patent_app_type] => new [patent_app_number] => 09/752594 [patent_app_country] => US [patent_app_date] => 2000-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11661 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20020080652.pdf [firstpage_image] =>[orig_patent_app_number] => 09752594 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/752594
Method and apparatus including special programming mode circuitry which disables internal program verification operations by a memory Dec 26, 2000 Issued
Array ( [id] => 6875726 [patent_doc_number] => 20010000820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-03 [patent_title] => 'Method and apparatus for detecting an initialization signal and a command packet error in packetized dynamic random access memories' [patent_app_type] => new-utility [patent_app_number] => 09/748955 [patent_app_country] => US [patent_app_date] => 2000-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10003 [patent_no_of_claims] => 71 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20010000820.pdf [firstpage_image] =>[orig_patent_app_number] => 09748955 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/748955
Method and apparatus for detecting an initialization signal and a command packet error in packetized dynamic random access memories Dec 25, 2000 Issued
Array ( [id] => 1490133 [patent_doc_number] => 06366992 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-04-02 [patent_title] => 'Method and system for bypassing pipelines in a pipelined memory command generator' [patent_app_type] => B2 [patent_app_number] => 09/748954 [patent_app_country] => US [patent_app_date] => 2000-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9377 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366992.pdf [firstpage_image] =>[orig_patent_app_number] => 09748954 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/748954
Method and system for bypassing pipelines in a pipelined memory command generator Dec 25, 2000 Issued
Array ( [id] => 1210346 [patent_doc_number] => 06718428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-06 [patent_title] => 'Storage array interconnection fabric using a torus topology' [patent_app_type] => B2 [patent_app_number] => 09/740132 [patent_app_country] => US [patent_app_date] => 2000-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4642 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/718/06718428.pdf [firstpage_image] =>[orig_patent_app_number] => 09740132 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/740132
Storage array interconnection fabric using a torus topology Dec 17, 2000 Issued
Array ( [id] => 6962814 [patent_doc_number] => 20010013086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-09 [patent_title] => 'Multiprocessor system and data transmitting method' [patent_app_type] => new [patent_app_number] => 09/736884 [patent_app_country] => US [patent_app_date] => 2000-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 11848 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20010013086.pdf [firstpage_image] =>[orig_patent_app_number] => 09736884 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/736884
Multiprocessor system and data transmitting method Dec 12, 2000 Abandoned
Array ( [id] => 1085012 [patent_doc_number] => 06834322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-21 [patent_title] => 'Nonvolatile semiconductor memory device having plural memory circuits selectively controlled by a master chip enable terminal or an input command and outputting a pass/fail result' [patent_app_type] => B2 [patent_app_number] => 09/731788 [patent_app_country] => US [patent_app_date] => 2000-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3985 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/834/06834322.pdf [firstpage_image] =>[orig_patent_app_number] => 09731788 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/731788
Nonvolatile semiconductor memory device having plural memory circuits selectively controlled by a master chip enable terminal or an input command and outputting a pass/fail result Dec 7, 2000 Issued
Array ( [id] => 1572403 [patent_doc_number] => 06378053 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Conserving storage space by means of low resolution objects' [patent_app_type] => B1 [patent_app_number] => 09/715985 [patent_app_country] => US [patent_app_date] => 2000-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7929 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/378/06378053.pdf [firstpage_image] =>[orig_patent_app_number] => 09715985 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/715985
Conserving storage space by means of low resolution objects Nov 19, 2000 Issued
Array ( [id] => 1210344 [patent_doc_number] => 06718427 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-06 [patent_title] => 'Method and system utilizing data fragments for efficiently importing/exporting removable storage volumes' [patent_app_type] => B1 [patent_app_number] => 09/694750 [patent_app_country] => US [patent_app_date] => 2000-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5246 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/718/06718427.pdf [firstpage_image] =>[orig_patent_app_number] => 09694750 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/694750
Method and system utilizing data fragments for efficiently importing/exporting removable storage volumes Oct 22, 2000 Issued
Array ( [id] => 1353245 [patent_doc_number] => 06594736 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'System and method for semaphore and atomic operation management in a multiprocessor' [patent_app_type] => B1 [patent_app_number] => 09/638365 [patent_app_country] => US [patent_app_date] => 2000-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4864 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/594/06594736.pdf [firstpage_image] =>[orig_patent_app_number] => 09638365 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/638365
System and method for semaphore and atomic operation management in a multiprocessor Aug 14, 2000 Issued
Array ( [id] => 1184658 [patent_doc_number] => 06748484 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-08 [patent_title] => 'Match resolution circuit for an associative memory' [patent_app_type] => B1 [patent_app_number] => 09/637131 [patent_app_country] => US [patent_app_date] => 2000-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4133 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/748/06748484.pdf [firstpage_image] =>[orig_patent_app_number] => 09637131 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/637131
Match resolution circuit for an associative memory Aug 9, 2000 Issued
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