Search

Dan Davidson

Examiner (ID: 17565)

Most Active Art Unit
2651
Art Unit(s)
2651, 2753, 2627
Total Applications
393
Issued Applications
356
Pending Applications
11
Abandoned Applications
26

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7644142 [patent_doc_number] => 06473832 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Load/store unit having pre-cache and post-cache queues for low latency load memory operations' [patent_app_type] => B1 [patent_app_number] => 09/314035 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 27587 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473832.pdf [firstpage_image] =>[orig_patent_app_number] => 09314035 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314035
Load/store unit having pre-cache and post-cache queues for low latency load memory operations May 17, 1999 Issued
Array ( [id] => 1587448 [patent_doc_number] => 06425066 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Integrated circuit comprising at least two memories' [patent_app_type] => B1 [patent_app_number] => 09/313926 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 4620 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425066.pdf [firstpage_image] =>[orig_patent_app_number] => 09313926 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/313926
Integrated circuit comprising at least two memories May 17, 1999 Issued
Array ( [id] => 1456635 [patent_doc_number] => 06457075 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Synchronous memory system with automatic burst mode switching as a function of the selected bus master' [patent_app_type] => B1 [patent_app_number] => 09/313244 [patent_app_country] => US [patent_app_date] => 1999-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4647 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457075.pdf [firstpage_image] =>[orig_patent_app_number] => 09313244 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/313244
Synchronous memory system with automatic burst mode switching as a function of the selected bus master May 16, 1999 Issued
Array ( [id] => 6019980 [patent_doc_number] => 20020103958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'PROGRAMMABLE NONVOLATILE MEMORY APPARATUS AND MICROCOMPUTER USING THE SAME' [patent_app_type] => new [patent_app_number] => 09/242961 [patent_app_country] => US [patent_app_date] => 1999-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6740 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20020103958.pdf [firstpage_image] =>[orig_patent_app_number] => 09242961 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/242961
Programmable nonvolatile memory apparatus and microcomputer using the same May 16, 1999 Issued
Array ( [id] => 1438669 [patent_doc_number] => 06356979 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'System and method for selectively presenting logical storage units to multiple host operating systems in a networked computing system' [patent_app_type] => B1 [patent_app_number] => 09/312944 [patent_app_country] => US [patent_app_date] => 1999-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 4450 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356979.pdf [firstpage_image] =>[orig_patent_app_number] => 09312944 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/312944
System and method for selectively presenting logical storage units to multiple host operating systems in a networked computing system May 16, 1999 Issued
Array ( [id] => 4138785 [patent_doc_number] => 06102539 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Sunglass lens laminate' [patent_app_type] => 1 [patent_app_number] => 9/313498 [patent_app_country] => US [patent_app_date] => 1999-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3949 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/102/06102539.pdf [firstpage_image] =>[orig_patent_app_number] => 313498 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/313498
Sunglass lens laminate May 16, 1999 Issued
Array ( [id] => 1505963 [patent_doc_number] => 06487632 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Emulation technique for variable-length disk system to access data in a fixed-length disk system' [patent_app_type] => B1 [patent_app_number] => 09/313781 [patent_app_country] => US [patent_app_date] => 1999-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4079 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/487/06487632.pdf [firstpage_image] =>[orig_patent_app_number] => 09313781 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/313781
Emulation technique for variable-length disk system to access data in a fixed-length disk system May 16, 1999 Issued
Array ( [id] => 4312191 [patent_doc_number] => 06237065 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Preemptive replacement strategy for a caching dynamic translator' [patent_app_type] => 1 [patent_app_number] => 9/312300 [patent_app_country] => US [patent_app_date] => 1999-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3917 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/237/06237065.pdf [firstpage_image] =>[orig_patent_app_number] => 312300 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/312300
Preemptive replacement strategy for a caching dynamic translator May 13, 1999 Issued
Array ( [id] => 4349604 [patent_doc_number] => 06321300 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Apparatus and method for dynamically reconfigurable timed flushing of a queue of coalescing write buffers' [patent_app_type] => 1 [patent_app_number] => 9/311987 [patent_app_country] => US [patent_app_date] => 1999-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3876 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321300.pdf [firstpage_image] =>[orig_patent_app_number] => 311987 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/311987
Apparatus and method for dynamically reconfigurable timed flushing of a queue of coalescing write buffers May 13, 1999 Issued
Array ( [id] => 1601965 [patent_doc_number] => 06385687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-07 [patent_title] => 'Method and apparatus for simultaneously accessing the tag and data arrays of a memory device' [patent_app_type] => B2 [patent_app_number] => 09/312122 [patent_app_country] => US [patent_app_date] => 1999-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3918 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385687.pdf [firstpage_image] =>[orig_patent_app_number] => 09312122 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/312122
Method and apparatus for simultaneously accessing the tag and data arrays of a memory device May 13, 1999 Issued
Array ( [id] => 4290325 [patent_doc_number] => 06308249 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Storing data in a grey code system' [patent_app_type] => 1 [patent_app_number] => 9/311954 [patent_app_country] => US [patent_app_date] => 1999-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3331 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/308/06308249.pdf [firstpage_image] =>[orig_patent_app_number] => 311954 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/311954
Storing data in a grey code system May 13, 1999 Issued
Array ( [id] => 4280815 [patent_doc_number] => 06260115 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Sequential detection and prestaging methods for a disk storage subsystem' [patent_app_type] => 1 [patent_app_number] => 9/311216 [patent_app_country] => US [patent_app_date] => 1999-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8854 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260115.pdf [firstpage_image] =>[orig_patent_app_number] => 311216 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/311216
Sequential detection and prestaging methods for a disk storage subsystem May 12, 1999 Issued
Array ( [id] => 4388087 [patent_doc_number] => 06275898 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Methods and structure for RAID level migration within a logical unit' [patent_app_type] => 1 [patent_app_number] => 9/311316 [patent_app_country] => US [patent_app_date] => 1999-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 9045 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275898.pdf [firstpage_image] =>[orig_patent_app_number] => 311316 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/311316
Methods and structure for RAID level migration within a logical unit May 12, 1999 Issued
Array ( [id] => 1429027 [patent_doc_number] => 06513105 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-28 [patent_title] => 'FIFO system with variable-width interface to host processor' [patent_app_type] => B1 [patent_app_number] => 09/307164 [patent_app_country] => US [patent_app_date] => 1999-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3727 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/513/06513105.pdf [firstpage_image] =>[orig_patent_app_number] => 09307164 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/307164
FIFO system with variable-width interface to host processor May 6, 1999 Issued
Array ( [id] => 1595864 [patent_doc_number] => 06484233 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Reproducing apparatus and method, program offering medium and storage medium' [patent_app_type] => B1 [patent_app_number] => 09/294662 [patent_app_country] => US [patent_app_date] => 1999-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 39 [patent_no_of_words] => 9116 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/484/06484233.pdf [firstpage_image] =>[orig_patent_app_number] => 09294662 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/294662
Reproducing apparatus and method, program offering medium and storage medium Apr 18, 1999 Issued
09/194937 DATA RECORDING DEVICE AND METHOD, AND DISK ARRAY CONTROL DEVICE AND METHOD Apr 15, 1999 Abandoned
Array ( [id] => 1549537 [patent_doc_number] => 06374324 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Flash memory array access method and device' [patent_app_type] => B1 [patent_app_number] => 09/271444 [patent_app_country] => US [patent_app_date] => 1999-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4209 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/374/06374324.pdf [firstpage_image] =>[orig_patent_app_number] => 09271444 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/271444
Flash memory array access method and device Mar 17, 1999 Issued
Array ( [id] => 1466231 [patent_doc_number] => 06393533 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Method and device for controlling access to memory' [patent_app_type] => B1 [patent_app_number] => 09/270613 [patent_app_country] => US [patent_app_date] => 1999-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2328 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393533.pdf [firstpage_image] =>[orig_patent_app_number] => 09270613 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/270613
Method and device for controlling access to memory Mar 16, 1999 Issued
Array ( [id] => 1431211 [patent_doc_number] => 06523099 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Integrated circuit with output inhibit feature and a control port to receive an inhibit release password' [patent_app_type] => B1 [patent_app_number] => 09/270779 [patent_app_country] => US [patent_app_date] => 1999-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4366 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/523/06523099.pdf [firstpage_image] =>[orig_patent_app_number] => 09270779 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/270779
Integrated circuit with output inhibit feature and a control port to receive an inhibit release password Mar 16, 1999 Issued
Array ( [id] => 4294714 [patent_doc_number] => 06324625 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Rotating rationed buffer refresh' [patent_app_type] => 1 [patent_app_number] => 9/270384 [patent_app_country] => US [patent_app_date] => 1999-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4515 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/324/06324625.pdf [firstpage_image] =>[orig_patent_app_number] => 270384 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/270384
Rotating rationed buffer refresh Mar 15, 1999 Issued
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