
Dan Davidson
Examiner (ID: 17565)
| Most Active Art Unit | 2651 |
| Art Unit(s) | 2651, 2753, 2627 |
| Total Applications | 393 |
| Issued Applications | 356 |
| Pending Applications | 11 |
| Abandoned Applications | 26 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
| 09/268365 | APPARATUS AND METHOD FOR DIRECT CONNECTION OF A MASS STORAGE DRIVE TO DIGITAL APPLIANCE | Mar 14, 1999 | Abandoned |
Array
(
[id] => 1258409
[patent_doc_number] => 06671787
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-12-30
[patent_title] => 'Semiconductor memory device and method of controlling the same'
[patent_app_type] => B2
[patent_app_number] => 09/264672
[patent_app_country] => US
[patent_app_date] => 1999-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 38
[patent_no_of_words] => 23753
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/671/06671787.pdf
[firstpage_image] =>[orig_patent_app_number] => 09264672
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/264672 | Semiconductor memory device and method of controlling the same | Mar 8, 1999 | Issued |
Array
(
[id] => 4351988
[patent_doc_number] => 06314504
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-06
[patent_title] => 'Multi-mode memory addressing using variable-length'
[patent_app_type] => 1
[patent_app_number] => 9/264795
[patent_app_country] => US
[patent_app_date] => 1999-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 7802
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/314/06314504.pdf
[firstpage_image] =>[orig_patent_app_number] => 264795
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/264795 | Multi-mode memory addressing using variable-length | Mar 8, 1999 | Issued |
Array
(
[id] => 4422480
[patent_doc_number] => 06272602
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-07
[patent_title] => 'Multiprocessing system employing pending tags to maintain cache coherence'
[patent_app_type] => 1
[patent_app_number] => 9/265233
[patent_app_country] => US
[patent_app_date] => 1999-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7612
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/272/06272602.pdf
[firstpage_image] =>[orig_patent_app_number] => 265233
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/265233 | Multiprocessing system employing pending tags to maintain cache coherence | Mar 7, 1999 | Issued |
Array
(
[id] => 4391775
[patent_doc_number] => 06289430
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-11
[patent_title] => 'Method and apparatus for target addressing and translation in a non-uniform memory environment with user defined target tags'
[patent_app_type] => 1
[patent_app_number] => 9/251029
[patent_app_country] => US
[patent_app_date] => 1999-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 2220
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/289/06289430.pdf
[firstpage_image] =>[orig_patent_app_number] => 251029
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/251029 | Method and apparatus for target addressing and translation in a non-uniform memory environment with user defined target tags | Feb 17, 1999 | Issued |
Array
(
[id] => 4325493
[patent_doc_number] => 06253294
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-26
[patent_title] => 'Shared device access protection'
[patent_app_type] => 1
[patent_app_number] => 9/252015
[patent_app_country] => US
[patent_app_date] => 1999-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 5821
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/253/06253294.pdf
[firstpage_image] =>[orig_patent_app_number] => 252015
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/252015 | Shared device access protection | Feb 17, 1999 | Issued |
Array
(
[id] => 7634979
[patent_doc_number] => 06381687
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-04-30
[patent_title] => 'Flexible memory channel'
[patent_app_type] => B2
[patent_app_number] => 09/252173
[patent_app_country] => US
[patent_app_date] => 1999-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 2975
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 7
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/381/06381687.pdf
[firstpage_image] =>[orig_patent_app_number] => 09252173
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/252173 | Flexible memory channel | Feb 17, 1999 | Issued |
Array
(
[id] => 1557562
[patent_doc_number] => 06401182
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-04
[patent_title] => 'Method and apparatus for memory management'
[patent_app_type] => B1
[patent_app_number] => 09/247495
[patent_app_country] => US
[patent_app_date] => 1999-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 19
[patent_no_of_words] => 4794
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/401/06401182.pdf
[firstpage_image] =>[orig_patent_app_number] => 09247495
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/247495 | Method and apparatus for memory management | Feb 9, 1999 | Issued |
Array
(
[id] => 1539237
[patent_doc_number] => 06412057
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-25
[patent_title] => 'Microprocessor with virtual-to-physical address translation using flags'
[patent_app_type] => B1
[patent_app_number] => 09/246407
[patent_app_country] => US
[patent_app_date] => 1999-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3525
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/412/06412057.pdf
[firstpage_image] =>[orig_patent_app_number] => 09246407
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/246407 | Microprocessor with virtual-to-physical address translation using flags | Feb 7, 1999 | Issued |
Array
(
[id] => 1552826
[patent_doc_number] => 06446159
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-03
[patent_title] => 'Semiconductor circuit and method of controlling the same'
[patent_app_type] => B1
[patent_app_number] => 09/242049
[patent_app_country] => US
[patent_app_date] => 1999-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 14
[patent_no_of_words] => 6664
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 36
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/446/06446159.pdf
[firstpage_image] =>[orig_patent_app_number] => 09242049
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/242049 | Semiconductor circuit and method of controlling the same | Feb 7, 1999 | Issued |
Array
(
[id] => 1604478
[patent_doc_number] => 06434664
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-13
[patent_title] => 'Data transfer scheme for efficiently moving data through a high latency media access channel'
[patent_app_type] => B1
[patent_app_number] => 09/244723
[patent_app_country] => US
[patent_app_date] => 1999-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 15
[patent_no_of_words] => 9307
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 216
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/434/06434664.pdf
[firstpage_image] =>[orig_patent_app_number] => 09244723
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/244723 | Data transfer scheme for efficiently moving data through a high latency media access channel | Feb 3, 1999 | Issued |
Array
(
[id] => 1466664
[patent_doc_number] => 06351792
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-26
[patent_title] => 'Selective remote storage copy system and methods'
[patent_app_type] => B1
[patent_app_number] => 09/243085
[patent_app_country] => US
[patent_app_date] => 1999-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2328
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/351/06351792.pdf
[firstpage_image] =>[orig_patent_app_number] => 09243085
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/243085 | Selective remote storage copy system and methods | Feb 1, 1999 | Issued |
Array
(
[id] => 1552877
[patent_doc_number] => 06446170
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-03
[patent_title] => 'Efficient store machine in cache based microprocessor'
[patent_app_type] => B1
[patent_app_number] => 09/232239
[patent_app_country] => US
[patent_app_date] => 1999-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 4291
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/446/06446170.pdf
[firstpage_image] =>[orig_patent_app_number] => 09232239
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/232239 | Efficient store machine in cache based microprocessor | Jan 18, 1999 | Issued |
Array
(
[id] => 4304648
[patent_doc_number] => 06269421
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-31
[patent_title] => 'Receiving apparatus and data rewriting method'
[patent_app_type] => 1
[patent_app_number] => 9/229199
[patent_app_country] => US
[patent_app_date] => 1999-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4331
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/269/06269421.pdf
[firstpage_image] =>[orig_patent_app_number] => 229199
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/229199 | Receiving apparatus and data rewriting method | Jan 12, 1999 | Issued |
Array
(
[id] => 4366146
[patent_doc_number] => 06286079
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-04
[patent_title] => 'Interruptible inventory of a mass data storage library'
[patent_app_type] => 1
[patent_app_number] => 9/228229
[patent_app_country] => US
[patent_app_date] => 1999-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 5045
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/286/06286079.pdf
[firstpage_image] =>[orig_patent_app_number] => 228229
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/228229 | Interruptible inventory of a mass data storage library | Jan 10, 1999 | Issued |
Array
(
[id] => 4351923
[patent_doc_number] => 06314500
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-06
[patent_title] => 'Selective routing of data in a multi-level memory architecture based on source identification information'
[patent_app_type] => 1
[patent_app_number] => 9/228314
[patent_app_country] => US
[patent_app_date] => 1999-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 8346
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/314/06314500.pdf
[firstpage_image] =>[orig_patent_app_number] => 228314
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/228314 | Selective routing of data in a multi-level memory architecture based on source identification information | Jan 10, 1999 | Issued |
Array
(
[id] => 4412303
[patent_doc_number] => 06298421
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-02
[patent_title] => 'Data storage device'
[patent_app_type] => 1
[patent_app_number] => 9/227898
[patent_app_country] => US
[patent_app_date] => 1999-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 14065
[patent_no_of_claims] => 50
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/298/06298421.pdf
[firstpage_image] =>[orig_patent_app_number] => 227898
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/227898 | Data storage device | Jan 10, 1999 | Issued |
Array
(
[id] => 4351974
[patent_doc_number] => 06314503
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-06
[patent_title] => 'Method and apparatus for managing the placement of data in a storage system to achieve increased system performance'
[patent_app_type] => 1
[patent_app_number] => 9/223092
[patent_app_country] => US
[patent_app_date] => 1998-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 12616
[patent_no_of_claims] => 83
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/314/06314503.pdf
[firstpage_image] =>[orig_patent_app_number] => 223092
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/223092 | Method and apparatus for managing the placement of data in a storage system to achieve increased system performance | Dec 29, 1998 | Issued |
Array
(
[id] => 1549569
[patent_doc_number] => 06374331
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-16
[patent_title] => 'Distributed directory cache coherence multi-processor computer architecture'
[patent_app_type] => B1
[patent_app_number] => 09/223469
[patent_app_country] => US
[patent_app_date] => 1998-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4598
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/374/06374331.pdf
[firstpage_image] =>[orig_patent_app_number] => 09223469
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/223469 | Distributed directory cache coherence multi-processor computer architecture | Dec 29, 1998 | Issued |
Array
(
[id] => 4294806
[patent_doc_number] => 06324632
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-27
[patent_title] => 'Processing a data stream'
[patent_app_type] => 1
[patent_app_number] => 9/223827
[patent_app_country] => US
[patent_app_date] => 1998-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 6019
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/324/06324632.pdf
[firstpage_image] =>[orig_patent_app_number] => 223827
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/223827 | Processing a data stream | Dec 29, 1998 | Issued |