Search

Dan Davidson

Examiner (ID: 15975)

Most Active Art Unit
2651
Art Unit(s)
2651, 2753, 2627
Total Applications
393
Issued Applications
356
Pending Applications
11
Abandoned Applications
26

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2163938 [patent_doc_number] => 04546538 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-10-15 [patent_title] => 'Method of manufacturing semiconductor integrated circuit devices having dielectric isolation regions' [patent_app_type] => 1 [patent_app_number] => 6/647827 [patent_app_country] => US [patent_app_date] => 1984-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 2584 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/546/04546538.pdf [firstpage_image] =>[orig_patent_app_number] => 647827 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/647827
Method of manufacturing semiconductor integrated circuit devices having dielectric isolation regions Sep 4, 1984 Issued
Array ( [id] => 2268970 [patent_doc_number] => 04622735 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-11-18 [patent_title] => 'Method for manufacturing a semiconductor device utilizing self-aligned silicide regions' [patent_app_type] => 1 [patent_app_number] => 6/645536 [patent_app_country] => US [patent_app_date] => 1984-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 36 [patent_no_of_words] => 7515 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/622/04622735.pdf [firstpage_image] =>[orig_patent_app_number] => 645536 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/645536
Method for manufacturing a semiconductor device utilizing self-aligned silicide regions Aug 28, 1984 Issued
Array ( [id] => 2173453 [patent_doc_number] => 04556436 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-12-03 [patent_title] => 'Method of preparing single crystalline cubic silicon carbide layers' [patent_app_type] => 1 [patent_app_number] => 6/643327 [patent_app_country] => US [patent_app_date] => 1984-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2107 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/556/04556436.pdf [firstpage_image] =>[orig_patent_app_number] => 643327 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/643327
Method of preparing single crystalline cubic silicon carbide layers Aug 21, 1984 Issued
Array ( [id] => 2238149 [patent_doc_number] => 04566918 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-01-28 [patent_title] => 'Utilizing interdiffusion of sequentially deposited links of HgTe and CdTe' [patent_app_type] => 1 [patent_app_number] => 6/641483 [patent_app_country] => US [patent_app_date] => 1984-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3444 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/566/04566918.pdf [firstpage_image] =>[orig_patent_app_number] => 641483 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/641483
Utilizing interdiffusion of sequentially deposited links of HgTe and CdTe Aug 15, 1984 Issued
Array ( [id] => 2249211 [patent_doc_number] => 04597167 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-07-01 [patent_title] => 'Method of forming a metal film on a selectively diffused layer' [patent_app_type] => 1 [patent_app_number] => 6/641191 [patent_app_country] => US [patent_app_date] => 1984-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2131 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/597/04597167.pdf [firstpage_image] =>[orig_patent_app_number] => 641191 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/641191
Method of forming a metal film on a selectively diffused layer Aug 15, 1984 Issued
Array ( [id] => 2298472 [patent_doc_number] => 04637129 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-01-20 [patent_title] => 'Selective area III-V growth and lift-off using tungsten patterning' [patent_app_type] => 1 [patent_app_number] => 6/635902 [patent_app_country] => US [patent_app_date] => 1984-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 7 [patent_no_of_words] => 2425 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/637/04637129.pdf [firstpage_image] =>[orig_patent_app_number] => 635902 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/635902
Selective area III-V growth and lift-off using tungsten patterning Jul 29, 1984 Issued
Array ( [id] => 2282361 [patent_doc_number] => 04586968 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-05-06 [patent_title] => 'Process of manufacturing a high frequency bipolar transistor utilizing doped silicide with self-aligned masking' [patent_app_type] => 1 [patent_app_number] => 6/628408 [patent_app_country] => US [patent_app_date] => 1984-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 1577 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/586/04586968.pdf [firstpage_image] =>[orig_patent_app_number] => 628408 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/628408
Process of manufacturing a high frequency bipolar transistor utilizing doped silicide with self-aligned masking Jul 5, 1984 Issued
Array ( [id] => 2288754 [patent_doc_number] => 04639277 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-01-27 [patent_title] => 'Semiconductor material on a substrate, said substrate comprising, in order, a layer of organic polymer, a layer of metal or metal alloy and a layer of dielectric material' [patent_app_type] => 1 [patent_app_number] => 6/626848 [patent_app_country] => US [patent_app_date] => 1984-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2378 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/639/04639277.pdf [firstpage_image] =>[orig_patent_app_number] => 626848 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/626848
Semiconductor material on a substrate, said substrate comprising, in order, a layer of organic polymer, a layer of metal or metal alloy and a layer of dielectric material Jul 1, 1984 Issued
Array ( [id] => 2159719 [patent_doc_number] => 04536947 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-08-27 [patent_title] => 'CMOS process for fabricating integrated circuits, particularly dynamic memory cells with storage capacitors' [patent_app_type] => 1 [patent_app_number] => 6/627061 [patent_app_country] => US [patent_app_date] => 1984-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 3690 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/536/04536947.pdf [firstpage_image] =>[orig_patent_app_number] => 627061 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/627061
CMOS process for fabricating integrated circuits, particularly dynamic memory cells with storage capacitors Jul 1, 1984 Issued
Array ( [id] => 2229532 [patent_doc_number] => 04575924 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-03-18 [patent_title] => 'Process for fabricating quantum-well devices utilizing etch and refill techniques' [patent_app_type] => 1 [patent_app_number] => 6/626809 [patent_app_country] => US [patent_app_date] => 1984-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 37 [patent_no_of_words] => 8615 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/575/04575924.pdf [firstpage_image] =>[orig_patent_app_number] => 626809 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/626809
Process for fabricating quantum-well devices utilizing etch and refill techniques Jul 1, 1984 Issued
Array ( [id] => 2173494 [patent_doc_number] => 04561916 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-12-31 [patent_title] => 'Method of growth of compound semiconductor' [patent_app_type] => 1 [patent_app_number] => 6/627031 [patent_app_country] => US [patent_app_date] => 1984-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2095 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/561/04561916.pdf [firstpage_image] =>[orig_patent_app_number] => 627031 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/627031
Method of growth of compound semiconductor Jul 1, 1984 Issued
Array ( [id] => 2144345 [patent_doc_number] => 04559086 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-12-17 [patent_title] => 'Backside gettering of silicon wafers utilizing selectively annealed single crystal silicon portions disposed between and extending into polysilicon portions' [patent_app_type] => 1 [patent_app_number] => 6/626849 [patent_app_country] => US [patent_app_date] => 1984-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2334 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/559/04559086.pdf [firstpage_image] =>[orig_patent_app_number] => 626849 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/626849
Backside gettering of silicon wafers utilizing selectively annealed single crystal silicon portions disposed between and extending into polysilicon portions Jul 1, 1984 Issued
Array ( [id] => 2214518 [patent_doc_number] => 04570330 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-02-18 [patent_title] => 'Method of producing isolated regions for an integrated circuit substrate' [patent_app_type] => 1 [patent_app_number] => 6/625390 [patent_app_country] => US [patent_app_date] => 1984-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2398 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 472 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/570/04570330.pdf [firstpage_image] =>[orig_patent_app_number] => 625390 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/625390
Method of producing isolated regions for an integrated circuit substrate Jun 27, 1984 Issued
Array ( [id] => 2173485 [patent_doc_number] => 04547231 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-10-15 [patent_title] => 'Method of manufacturing semiconductor device utilizing selective epitaxial growth under reduced pressure' [patent_app_type] => 1 [patent_app_number] => 6/625783 [patent_app_country] => US [patent_app_date] => 1984-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 1395 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/547/04547231.pdf [firstpage_image] =>[orig_patent_app_number] => 625783 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/625783
Method of manufacturing semiconductor device utilizing selective epitaxial growth under reduced pressure Jun 25, 1984 Issued
Array ( [id] => 2197901 [patent_doc_number] => 04528047 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-07-09 [patent_title] => 'Method for forming a void free isolation structure utilizing etch and refill techniques' [patent_app_type] => 1 [patent_app_number] => 6/624425 [patent_app_country] => US [patent_app_date] => 1984-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4797 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/528/04528047.pdf [firstpage_image] =>[orig_patent_app_number] => 624425 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/624425
Method for forming a void free isolation structure utilizing etch and refill techniques Jun 24, 1984 Issued
Array ( [id] => 2195708 [patent_doc_number] => 04526631 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-07-02 [patent_title] => 'Method for forming a void free isolation pattern utilizing etch and refill techniques' [patent_app_type] => 1 [patent_app_number] => 6/624320 [patent_app_country] => US [patent_app_date] => 1984-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4274 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/526/04526631.pdf [firstpage_image] =>[orig_patent_app_number] => 624320 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/624320
Method for forming a void free isolation pattern utilizing etch and refill techniques Jun 24, 1984 Issued
Array ( [id] => 2140526 [patent_doc_number] => 04538343 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-09-03 [patent_title] => 'Channel stop isolation technology utilizing two-step etching and selective oxidation with sidewall masking' [patent_app_type] => 1 [patent_app_number] => 6/620995 [patent_app_country] => US [patent_app_date] => 1984-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 4777 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/538/04538343.pdf [firstpage_image] =>[orig_patent_app_number] => 620995 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/620995
Channel stop isolation technology utilizing two-step etching and selective oxidation with sidewall masking Jun 14, 1984 Issued
Array ( [id] => 2162951 [patent_doc_number] => 04561172 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-12-31 [patent_title] => 'Integrated circuit fabrication method utilizing selective etching and oxidation to form isolation regions' [patent_app_type] => 1 [patent_app_number] => 6/621023 [patent_app_country] => US [patent_app_date] => 1984-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 3953 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/561/04561172.pdf [firstpage_image] =>[orig_patent_app_number] => 621023 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/621023
Integrated circuit fabrication method utilizing selective etching and oxidation to form isolation regions Jun 14, 1984 Issued
Array ( [id] => 2260169 [patent_doc_number] => 04579609 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-04-01 [patent_title] => 'Growth of epitaxial films by chemical vapor deposition utilizing a surface cleaning step immediately before deposition' [patent_app_type] => 1 [patent_app_number] => 6/618592 [patent_app_country] => US [patent_app_date] => 1984-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3842 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/579/04579609.pdf [firstpage_image] =>[orig_patent_app_number] => 618592 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/618592
Growth of epitaxial films by chemical vapor deposition utilizing a surface cleaning step immediately before deposition Jun 7, 1984 Issued
Array ( [id] => 2277974 [patent_doc_number] => 04651408 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-03-24 [patent_title] => 'Fabrication of stacked MOS devices utilizing lateral seeding and a plurality of separate implants at different energies' [patent_app_type] => 1 [patent_app_number] => 6/611549 [patent_app_country] => US [patent_app_date] => 1984-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 21 [patent_no_of_words] => 3569 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/651/04651408.pdf [firstpage_image] =>[orig_patent_app_number] => 611549 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/611549
Fabrication of stacked MOS devices utilizing lateral seeding and a plurality of separate implants at different energies May 16, 1984 Issued
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