
Dan Davidson
Examiner (ID: 15975)
| Most Active Art Unit | 2651 |
| Art Unit(s) | 2651, 2753, 2627 |
| Total Applications | 393 |
| Issued Applications | 356 |
| Pending Applications | 11 |
| Abandoned Applications | 26 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2165658
[patent_doc_number] => 04512074
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-04-23
[patent_title] => 'Method for manufacturing a semiconductor device utilizing selective oxidation and diffusion from a polycrystalline source'
[patent_app_type] => 1
[patent_app_number] => 6/528793
[patent_app_country] => US
[patent_app_date] => 1983-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 3136
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/512/04512074.pdf
[firstpage_image] =>[orig_patent_app_number] => 528793
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/528793 | Method for manufacturing a semiconductor device utilizing selective oxidation and diffusion from a polycrystalline source | Sep 1, 1983 | Issued |
Array
(
[id] => 2185387
[patent_doc_number] => 04502208
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-03-05
[patent_title] => 'Method of making high density VMOS electrically-programmable ROM'
[patent_app_type] => 1
[patent_app_number] => 6/526515
[patent_app_country] => US
[patent_app_date] => 1983-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 2081
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/502/04502208.pdf
[firstpage_image] =>[orig_patent_app_number] => 526515
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/526515 | Method of making high density VMOS electrically-programmable ROM | Aug 25, 1983 | Issued |
Array
(
[id] => 2152369
[patent_doc_number] => 04499656
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-02-19
[patent_title] => 'Deep mesa process for fabricating monolithic integrated Schottky barrier diode for millimeter wave mixers'
[patent_app_type] => 1
[patent_app_number] => 6/523232
[patent_app_country] => US
[patent_app_date] => 1983-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 3867
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 292
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/499/04499656.pdf
[firstpage_image] =>[orig_patent_app_number] => 523232
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/523232 | Deep mesa process for fabricating monolithic integrated Schottky barrier diode for millimeter wave mixers | Aug 14, 1983 | Issued |
Array
(
[id] => 2108363
[patent_doc_number] => 04467521
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-08-28
[patent_title] => 'Selective epitaxial growth of gallium arsenide with selective orientation'
[patent_app_type] => 1
[patent_app_number] => 6/523506
[patent_app_country] => US
[patent_app_date] => 1983-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2260
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 286
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/467/04467521.pdf
[firstpage_image] =>[orig_patent_app_number] => 523506
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/523506 | Selective epitaxial growth of gallium arsenide with selective orientation | Aug 14, 1983 | Issued |
Array
(
[id] => 2176502
[patent_doc_number] => 04507158
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-03-26
[patent_title] => 'Trench isolated transistors in semiconductor films'
[patent_app_type] => 1
[patent_app_number] => 6/522767
[patent_app_country] => US
[patent_app_date] => 1983-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 792
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/507/04507158.pdf
[firstpage_image] =>[orig_patent_app_number] => 522767
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/522767 | Trench isolated transistors in semiconductor films | Aug 11, 1983 | Issued |
Array
(
[id] => 2139238
[patent_doc_number] => 04522662
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-06-11
[patent_title] => 'CVD lateral epitaxial growth of silicon over insulators'
[patent_app_type] => 1
[patent_app_number] => 6/522804
[patent_app_country] => US
[patent_app_date] => 1983-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 1529
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/522/04522662.pdf
[firstpage_image] =>[orig_patent_app_number] => 522804
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/522804 | CVD lateral epitaxial growth of silicon over insulators | Aug 11, 1983 | Issued |
Array
(
[id] => 2165677
[patent_doc_number] => 04512075
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-04-23
[patent_title] => 'Method of making an integrated injection logic cell having self-aligned collector and base reduced resistance utilizing selective diffusion from polycrystalline regions'
[patent_app_type] => 1
[patent_app_number] => 6/517564
[patent_app_country] => US
[patent_app_date] => 1983-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 9
[patent_no_of_words] => 2642
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 350
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/512/04512075.pdf
[firstpage_image] =>[orig_patent_app_number] => 517564
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/517564 | Method of making an integrated injection logic cell having self-aligned collector and base reduced resistance utilizing selective diffusion from polycrystalline regions | Jul 27, 1983 | Issued |
Array
(
[id] => 2135410
[patent_doc_number] => 04505026
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-03-19
[patent_title] => 'CMOS Process for fabricating integrated circuits, particularly dynamic memory cells'
[patent_app_type] => 1
[patent_app_number] => 6/513658
[patent_app_country] => US
[patent_app_date] => 1983-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 18
[patent_no_of_words] => 3708
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/505/04505026.pdf
[firstpage_image] =>[orig_patent_app_number] => 513658
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/513658 | CMOS Process for fabricating integrated circuits, particularly dynamic memory cells | Jul 13, 1983 | Issued |
Array
(
[id] => 2164524
[patent_doc_number] => 04528745
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-07-16
[patent_title] => 'Method for the formation of buried gates of a semiconductor device utilizing etch and refill techniques'
[patent_app_type] => 1
[patent_app_number] => 6/511193
[patent_app_country] => US
[patent_app_date] => 1983-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 31
[patent_no_of_words] => 5672
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/528/04528745.pdf
[firstpage_image] =>[orig_patent_app_number] => 511193
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/511193 | Method for the formation of buried gates of a semiconductor device utilizing etch and refill techniques | Jul 5, 1983 | Issued |
Array
(
[id] => 2133837
[patent_doc_number] => 04498227
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-02-12
[patent_title] => 'Wafer fabrication by implanting through protective layer'
[patent_app_type] => 1
[patent_app_number] => 6/510761
[patent_app_country] => US
[patent_app_date] => 1983-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 7105
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 458
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/498/04498227.pdf
[firstpage_image] =>[orig_patent_app_number] => 510761
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/510761 | Wafer fabrication by implanting through protective layer | Jul 4, 1983 | Issued |
Array
(
[id] => 2139229
[patent_doc_number] => 04522661
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-06-11
[patent_title] => 'Low defect, high purity crystalline layers grown by selective deposition'
[patent_app_type] => 1
[patent_app_number] => 6/507624
[patent_app_country] => US
[patent_app_date] => 1983-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 6
[patent_no_of_words] => 2111
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/522/04522661.pdf
[firstpage_image] =>[orig_patent_app_number] => 507624
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/507624 | Low defect, high purity crystalline layers grown by selective deposition | Jun 23, 1983 | Issued |
Array
(
[id] => 2227544
[patent_doc_number] => 04566171
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-01-28
[patent_title] => 'Elimination of mask undercutting in the fabrication of InP/InGaAsP BH devices'
[patent_app_type] => 1
[patent_app_number] => 6/505993
[patent_app_country] => US
[patent_app_date] => 1983-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 3797
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/566/04566171.pdf
[firstpage_image] =>[orig_patent_app_number] => 505993
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/505993 | Elimination of mask undercutting in the fabrication of InP/InGaAsP BH devices | Jun 19, 1983 | Issued |
Array
(
[id] => 2106332
[patent_doc_number] => 04484388
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-11-27
[patent_title] => 'Method for manufacturing semiconductor Bi-CMOS device'
[patent_app_type] => 1
[patent_app_number] => 6/504161
[patent_app_country] => US
[patent_app_date] => 1983-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 19
[patent_no_of_words] => 5988
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 363
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/484/04484388.pdf
[firstpage_image] =>[orig_patent_app_number] => 504161
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/504161 | Method for manufacturing semiconductor Bi-CMOS device | Jun 13, 1983 | Issued |
Array
(
[id] => 2125947
[patent_doc_number] => 04490192
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-12-25
[patent_title] => 'Stable suspensions of boron, phosphorus, antimony and arsenic dopants'
[patent_app_type] => 1
[patent_app_number] => 6/502360
[patent_app_country] => US
[patent_app_date] => 1983-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4966
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/490/04490192.pdf
[firstpage_image] =>[orig_patent_app_number] => 502360
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/502360 | Stable suspensions of boron, phosphorus, antimony and arsenic dopants | Jun 7, 1983 | Issued |
Array
(
[id] => 2201098
[patent_doc_number] => 04544417
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-10-01
[patent_title] => 'Transient capless annealing process for the activation of ion implanted compound semiconductors'
[patent_app_type] => 1
[patent_app_number] => 6/499083
[patent_app_country] => US
[patent_app_date] => 1983-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3926
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/544/04544417.pdf
[firstpage_image] =>[orig_patent_app_number] => 499083
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/499083 | Transient capless annealing process for the activation of ion implanted compound semiconductors | May 26, 1983 | Issued |
Array
(
[id] => 2241531
[patent_doc_number] => 04632710
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-12-30
[patent_title] => 'Vapor phase epitaxial growth of carbon doped layers of Group III-V materials'
[patent_app_type] => 1
[patent_app_number] => 6/493172
[patent_app_country] => US
[patent_app_date] => 1983-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 6410
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/632/04632710.pdf
[firstpage_image] =>[orig_patent_app_number] => 493172
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/493172 | Vapor phase epitaxial growth of carbon doped layers of Group III-V materials | May 9, 1983 | Issued |
Array
(
[id] => 2142784
[patent_doc_number] => 04505766
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-03-19
[patent_title] => 'Method of fabricating a semiconductor device utilizing simultaneous outdiffusion and epitaxial deposition'
[patent_app_type] => 1
[patent_app_number] => 6/491543
[patent_app_country] => US
[patent_app_date] => 1983-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 19
[patent_no_of_words] => 3843
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 281
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/505/04505766.pdf
[firstpage_image] =>[orig_patent_app_number] => 491543
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/491543 | Method of fabricating a semiconductor device utilizing simultaneous outdiffusion and epitaxial deposition | May 3, 1983 | Issued |
Array
(
[id] => 2272198
[patent_doc_number] => 04586238
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-05-06
[patent_title] => 'Method of manufacturing field-effect transistors utilizing self-aligned techniques'
[patent_app_type] => 1
[patent_app_number] => 6/487085
[patent_app_country] => US
[patent_app_date] => 1983-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 54
[patent_no_of_words] => 20750
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/586/04586238.pdf
[firstpage_image] =>[orig_patent_app_number] => 487085
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/487085 | Method of manufacturing field-effect transistors utilizing self-aligned techniques | Apr 20, 1983 | Issued |
Array
(
[id] => 2176075
[patent_doc_number] => 04512825
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-04-23
[patent_title] => 'Recovery of fragile layers produced on substrates by chemical vapor deposition'
[patent_app_type] => 1
[patent_app_number] => 6/484346
[patent_app_country] => US
[patent_app_date] => 1983-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 1826
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/512/04512825.pdf
[firstpage_image] =>[orig_patent_app_number] => 484346
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/484346 | Recovery of fragile layers produced on substrates by chemical vapor deposition | Apr 11, 1983 | Issued |
Array
(
[id] => 2088585
[patent_doc_number] => 04473938
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-10-02
[patent_title] => 'Method for making a GaN electroluminescent semiconductor device utilizing epitaxial deposition'
[patent_app_type] => 1
[patent_app_number] => 6/484374
[patent_app_country] => US
[patent_app_date] => 1983-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 2203
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/473/04473938.pdf
[firstpage_image] =>[orig_patent_app_number] => 484374
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/484374 | Method for making a GaN electroluminescent semiconductor device utilizing epitaxial deposition | Apr 11, 1983 | Issued |