Search

Dana Lynne Meyrow

Examiner (ID: 11885, Phone: (571)272-6034 , Office: P/2916 )

Most Active Art Unit
2916
Art Unit(s)
2912, 2916
Total Applications
2854
Issued Applications
2822
Pending Applications
0
Abandoned Applications
30

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11694574 [patent_doc_number] => 20170170291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'EPI FACET HEIGHT UNIFORMITY IMPROVEMENT FOR FDSOI TECHNOLOGIES' [patent_app_type] => utility [patent_app_number] => 14/963397 [patent_app_country] => US [patent_app_date] => 2015-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3111 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14963397 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/963397
Epi facet height uniformity improvement for FDSOI technologies Dec 8, 2015 Issued
Array ( [id] => 10982037 [patent_doc_number] => 20160178981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'FRINGE FIELD SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/963481 [patent_app_country] => US [patent_app_date] => 2015-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5991 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14963481 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/963481
Fringe field switching mode liquid crystal display device Dec 8, 2015 Issued
Array ( [id] => 11694580 [patent_doc_number] => 20170170297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'DUAL ISOLATION FIN AND METHOD OF MAKING' [patent_app_type] => utility [patent_app_number] => 14/963446 [patent_app_country] => US [patent_app_date] => 2015-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4207 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14963446 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/963446
Dual isolation fin and method of making Dec 8, 2015 Issued
Array ( [id] => 10817531 [patent_doc_number] => 20160163695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'Integrated Circuit Comprising Group III-N Transistors Monolithically Integrated on a Silicon Substrate and a Method for Manufacturing Thereof' [patent_app_type] => utility [patent_app_number] => 14/963650 [patent_app_country] => US [patent_app_date] => 2015-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2931 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14963650 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/963650
Integrated Circuit Comprising Group III-N Transistors Monolithically Integrated on a Silicon Substrate and a Method for Manufacturing Thereof Dec 8, 2015 Abandoned
Array ( [id] => 10817573 [patent_doc_number] => 20160163736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'GATE ARRAY FOR HIGH-SPEED CMOS AND HIGH-SPEED CMOS TTL FAMILY' [patent_app_type] => utility [patent_app_number] => 14/963622 [patent_app_country] => US [patent_app_date] => 2015-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2018 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14963622 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/963622
GATE ARRAY FOR HIGH-SPEED CMOS AND HIGH-SPEED CMOS TTL FAMILY Dec 8, 2015 Abandoned
Array ( [id] => 11110843 [patent_doc_number] => 20160307813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-20 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/963701 [patent_app_country] => US [patent_app_date] => 2015-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5177 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14963701 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/963701
Semiconductor device for reducing self-inductance Dec 8, 2015 Issued
Array ( [id] => 13862215 [patent_doc_number] => 10192833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-29 [patent_title] => Interposer and semiconductor package with noise suppression features [patent_app_type] => utility [patent_app_number] => 14/943063 [patent_app_country] => US [patent_app_date] => 2015-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6276 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14943063 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/943063
Interposer and semiconductor package with noise suppression features Nov 16, 2015 Issued
Array ( [id] => 11350020 [patent_doc_number] => 20160368760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'MEMS CHIP PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/940167 [patent_app_country] => US [patent_app_date] => 2015-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3355 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14940167 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/940167
MEMS chip package Nov 12, 2015 Issued
Array ( [id] => 11346416 [patent_doc_number] => 09530832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-27 [patent_title] => 'Electro-optical device and electronic apparatus' [patent_app_type] => utility [patent_app_number] => 14/939383 [patent_app_country] => US [patent_app_date] => 2015-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9717 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14939383 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/939383
Electro-optical device and electronic apparatus Nov 11, 2015 Issued
Array ( [id] => 12054415 [patent_doc_number] => 20170330760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'Method for Manufacturing Pillar or Hole Structures in a Layer of a Semiconductor Device, and Associated Semiconductor Structure' [patent_app_type] => utility [patent_app_number] => 15/520742 [patent_app_country] => US [patent_app_date] => 2015-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6505 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15520742 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/520742
Method for Manufacturing Pillar or Hole Structures in a Layer of a Semiconductor Device, and Associated Semiconductor Structure Oct 27, 2015 Abandoned
Array ( [id] => 10697055 [patent_doc_number] => 20160043202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-11 [patent_title] => 'SELF-ALIGNED BIPOLAR JUNCTION TRANSISTOR HAVING SELF-PLANARIZING ISOLATION RAISED BASE STRUCTURES' [patent_app_type] => utility [patent_app_number] => 14/922457 [patent_app_country] => US [patent_app_date] => 2015-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5275 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14922457 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/922457
SELF-ALIGNED BIPOLAR JUNCTION TRANSISTOR HAVING SELF-PLANARIZING ISOLATION RAISED BASE STRUCTURES Oct 25, 2015 Abandoned
Array ( [id] => 15139539 [patent_doc_number] => 10483256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Optoelectronic semiconductor device and apparatus with an optoelectronic semiconductor device [patent_app_type] => utility [patent_app_number] => 15/520666 [patent_app_country] => US [patent_app_date] => 2015-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5600 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15520666 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/520666
Optoelectronic semiconductor device and apparatus with an optoelectronic semiconductor device Oct 20, 2015 Issued
Array ( [id] => 12027152 [patent_doc_number] => 20170317251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'DIRECTIONAL LIGHT EMITTING ARRANGEMENT AND A METHOD OF PRODUCING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/520782 [patent_app_country] => US [patent_app_date] => 2015-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7456 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15520782 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/520782
Directional light emitting arrangement and a method of producing the same Oct 19, 2015 Issued
Array ( [id] => 10697074 [patent_doc_number] => 20160043221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-11 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/885925 [patent_app_country] => US [patent_app_date] => 2015-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 10129 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14885925 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/885925
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Oct 15, 2015 Abandoned
Array ( [id] => 10681734 [patent_doc_number] => 20160027879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-28 [patent_title] => 'DISCLOCATION IN SiC SEMICONDUCTOR SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 14/873471 [patent_app_country] => US [patent_app_date] => 2015-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8632 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14873471 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/873471
Dislocation in SiC semiconductor substrate Oct 1, 2015 Issued
Array ( [id] => 13541723 [patent_doc_number] => 20180322408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => CO-PLANAR WAVEGUIDE FLUX QUBITS [patent_app_type] => utility [patent_app_number] => 15/764021 [patent_app_country] => US [patent_app_date] => 2015-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15764021 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/764021
Co-planar waveguide flux qubits Sep 29, 2015 Issued
Array ( [id] => 13349905 [patent_doc_number] => 20180226492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => LONG CHANNEL MOS TRANSISTORS FOR LOW LEAKAGE APPLICATIONS ON A SHORT CHANNEL CMOS CHIP [patent_app_type] => utility [patent_app_number] => 15/748842 [patent_app_country] => US [patent_app_date] => 2015-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8816 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15748842 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/748842
Long channel MOS transistors for low leakage applications on a short channel CMOS chip Sep 24, 2015 Issued
Array ( [id] => 10667113 [patent_doc_number] => 20160013258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'ELECTRO-OPTICAL DEVICE AND ELECTRONIC APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/865695 [patent_app_country] => US [patent_app_date] => 2015-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7546 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14865695 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/865695
Electro-optical device and electronic apparatus Sep 24, 2015 Issued
Array ( [id] => 15519719 [patent_doc_number] => 10566458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-18 [patent_title] => Array substrate and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 14/897677 [patent_app_country] => US [patent_app_date] => 2015-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3652 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14897677 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/897677
Array substrate and method for manufacturing the same Aug 31, 2015 Issued
Array ( [id] => 10472281 [patent_doc_number] => 20150357296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'HYBRID BONDING MECHANISMS FOR SEMICONDUCTOR WAFERS' [patent_app_type] => utility [patent_app_number] => 14/830820 [patent_app_country] => US [patent_app_date] => 2015-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6369 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14830820 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/830820
Hybrid bonding mechanisms for semiconductor wafers Aug 19, 2015 Issued
Menu