Dana Lynne Meyrow
Examiner (ID: 11885, Phone: (571)272-6034 , Office: P/2916 )
Most Active Art Unit | 2916 |
Art Unit(s) | 2912, 2916 |
Total Applications | 2854 |
Issued Applications | 2822 |
Pending Applications | 0 |
Abandoned Applications | 30 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 11694574
[patent_doc_number] => 20170170291
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-15
[patent_title] => 'EPI FACET HEIGHT UNIFORMITY IMPROVEMENT FOR FDSOI TECHNOLOGIES'
[patent_app_type] => utility
[patent_app_number] => 14/963397
[patent_app_country] => US
[patent_app_date] => 2015-12-09
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/963397 | Epi facet height uniformity improvement for FDSOI technologies | Dec 8, 2015 | Issued |
Array
(
[id] => 10982037
[patent_doc_number] => 20160178981
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[patent_kind] => A1
[patent_issue_date] => 2016-06-23
[patent_title] => 'FRINGE FIELD SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/963481
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/963481 | Fringe field switching mode liquid crystal display device | Dec 8, 2015 | Issued |
Array
(
[id] => 11694580
[patent_doc_number] => 20170170297
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-15
[patent_title] => 'DUAL ISOLATION FIN AND METHOD OF MAKING'
[patent_app_type] => utility
[patent_app_number] => 14/963446
[patent_app_country] => US
[patent_app_date] => 2015-12-09
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[patent_drawing_sheets_cnt] => 9
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Array
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[patent_kind] => A1
[patent_issue_date] => 2016-06-09
[patent_title] => 'Integrated Circuit Comprising Group III-N Transistors Monolithically Integrated on a Silicon Substrate and a Method for Manufacturing Thereof'
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[patent_app_number] => 14/963650
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Array
(
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[patent_doc_number] => 20160163736
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[patent_title] => 'GATE ARRAY FOR HIGH-SPEED CMOS AND HIGH-SPEED CMOS TTL FAMILY'
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[patent_app_number] => 14/963622
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Array
(
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[patent_issue_date] => 2016-10-20
[patent_title] => 'SEMICONDUCTOR DEVICE'
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Array
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[patent_kind] => B2
[patent_issue_date] => 2019-01-29
[patent_title] => Interposer and semiconductor package with noise suppression features
[patent_app_type] => utility
[patent_app_number] => 14/943063
[patent_app_country] => US
[patent_app_date] => 2015-11-17
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[patent_drawing_sheets_cnt] => 15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/943063 | Interposer and semiconductor package with noise suppression features | Nov 16, 2015 | Issued |
Array
(
[id] => 11350020
[patent_doc_number] => 20160368760
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[patent_kind] => A1
[patent_issue_date] => 2016-12-22
[patent_title] => 'MEMS CHIP PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 14/940167
[patent_app_country] => US
[patent_app_date] => 2015-11-13
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[patent_drawing_sheets_cnt] => 4
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/940167 | MEMS chip package | Nov 12, 2015 | Issued |
Array
(
[id] => 11346416
[patent_doc_number] => 09530832
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-12-27
[patent_title] => 'Electro-optical device and electronic apparatus'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/939383 | Electro-optical device and electronic apparatus | Nov 11, 2015 | Issued |
Array
(
[id] => 12054415
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[patent_issue_date] => 2017-11-16
[patent_title] => 'Method for Manufacturing Pillar or Hole Structures in a Layer of a Semiconductor Device, and Associated Semiconductor Structure'
[patent_app_type] => utility
[patent_app_number] => 15/520742
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/520742 | Method for Manufacturing Pillar or Hole Structures in a Layer of a Semiconductor Device, and Associated Semiconductor Structure | Oct 27, 2015 | Abandoned |
Array
(
[id] => 10697055
[patent_doc_number] => 20160043202
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[patent_issue_date] => 2016-02-11
[patent_title] => 'SELF-ALIGNED BIPOLAR JUNCTION TRANSISTOR HAVING SELF-PLANARIZING ISOLATION RAISED BASE STRUCTURES'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/922457 | SELF-ALIGNED BIPOLAR JUNCTION TRANSISTOR HAVING SELF-PLANARIZING ISOLATION RAISED BASE STRUCTURES | Oct 25, 2015 | Abandoned |
Array
(
[id] => 15139539
[patent_doc_number] => 10483256
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[patent_kind] => B2
[patent_issue_date] => 2019-11-19
[patent_title] => Optoelectronic semiconductor device and apparatus with an optoelectronic semiconductor device
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Array
(
[id] => 12027152
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Array
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Array
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Array
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Array
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Array
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Array
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