Dana Lynne Meyrow

Array ( [id] => 19037845 [patent_doc_number] => 20240087660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => OTP MEMORY DEVICE, METHOD FOR OPERATING SAME AND METHOD FOR FABRICATING SAME [patent_app_type] => utility [patent_app_number] => 17/953717 [patent_app_country] => US [patent_app_date] => 2022-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5757 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17953717 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19726910 [patent_doc_number] => 20250029661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => FLASH MEMORY ARRAY, AND WRITING METHOD AND ERASING METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 18/686611 [patent_app_country] => US [patent_app_date] => 2022-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17797 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18686611 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18820842 [patent_doc_number] => 20230395183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => ERROR DETECTION FOR A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/889369 [patent_app_country] => US [patent_app_date] => 2022-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8536 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17889369 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20745677 [patent_doc_number] => 12645589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-02 [patent_title] => Half latch level shifting circuit for non-volatile memory architectures [patent_app_type] => utility [patent_app_number] => 17/831236 [patent_app_country] => US [patent_app_date] => 2022-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12186 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17831236 [rel_patent_id] =>[rel_patent_doc_number] =>)