Search

Dana Lynne Meyrow

Examiner (ID: 11885, Phone: (571)272-6034 , Office: P/2916 )

Most Active Art Unit
2916
Art Unit(s)
2912, 2916
Total Applications
2854
Issued Applications
2822
Pending Applications
0
Abandoned Applications
30

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12033935 [patent_doc_number] => 20170324034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'RESISTIVE MEMORY HAVING CONFINED FILAMENT FORMATION' [patent_app_type] => utility [patent_app_number] => 15/661351 [patent_app_country] => US [patent_app_date] => 2017-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4746 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15661351 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/661351
Resistive memory having confined filament formation Jul 26, 2017 Issued
Array ( [id] => 13769681 [patent_doc_number] => 10177190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Solid-state image pickup device [patent_app_type] => utility [patent_app_number] => 15/656979 [patent_app_country] => US [patent_app_date] => 2017-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7729 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15656979 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/656979
Solid-state image pickup device Jul 20, 2017 Issued
Array ( [id] => 15315521 [patent_doc_number] => 10522476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Package structure, integrated fan-out package and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 15/652247 [patent_app_country] => US [patent_app_date] => 2017-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 6401 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15652247 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/652247
Package structure, integrated fan-out package and method of fabricating the same Jul 17, 2017 Issued
Array ( [id] => 12141253 [patent_doc_number] => 20180019335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'GRADED AND STEPPED EPITAXY FOR CONSTRUCTING POWER CIRCUITS AND DEVICES' [patent_app_type] => utility [patent_app_number] => 15/652085 [patent_app_country] => US [patent_app_date] => 2017-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5133 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15652085 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/652085
GRADED AND STEPPED EPITAXY FOR CONSTRUCTING POWER CIRCUITS AND DEVICES Jul 16, 2017 Abandoned
Array ( [id] => 12141226 [patent_doc_number] => 20180019309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'SEMICONDUCTOR DEVICE BASED ON WIDEBAND GAP SEMICONDUCTOR MATERIALS' [patent_app_type] => utility [patent_app_number] => 15/652112 [patent_app_country] => US [patent_app_date] => 2017-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5905 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15652112 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/652112
SEMICONDUCTOR DEVICE BASED ON WIDEBAND GAP SEMICONDUCTOR MATERIALS Jul 16, 2017 Abandoned
Array ( [id] => 15857559 [patent_doc_number] => 10644081 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Flexible display apparatus and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 15/644010 [patent_app_country] => US [patent_app_date] => 2017-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 5261 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15644010 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/644010
Flexible display apparatus and method of fabricating the same Jul 6, 2017 Issued
Array ( [id] => 13598501 [patent_doc_number] => 20180350799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => SEMICONDUCTOR STRUCTURE WITH A RESISTOR AND A TRANSISTOR AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 15/608374 [patent_app_country] => US [patent_app_date] => 2017-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15608374 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/608374
Semiconductor structure with a resistor and a transistor and method for forming the same May 29, 2017 Issued
Array ( [id] => 13598293 [patent_doc_number] => 20180350695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => VERTICAL FIELD EFFECT TRANSISTOR (FET) WITH CONTROLLABLE GATE LENGTH [patent_app_type] => utility [patent_app_number] => 15/608159 [patent_app_country] => US [patent_app_date] => 2017-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15608159 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/608159
Vertical field effect transistor (FET) with controllable gate length May 29, 2017 Issued
Array ( [id] => 13769857 [patent_doc_number] => 10177279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Light-emitting diode with multiple N contact structure [patent_app_type] => utility [patent_app_number] => 15/608141 [patent_app_country] => US [patent_app_date] => 2017-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 6356 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15608141 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/608141
Light-emitting diode with multiple N contact structure May 29, 2017 Issued
Array ( [id] => 15170263 [patent_doc_number] => 10490637 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Semiconductor devices including an active fin and a drift region [patent_app_type] => utility [patent_app_number] => 15/608395 [patent_app_country] => US [patent_app_date] => 2017-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 34 [patent_no_of_words] => 13501 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15608395 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/608395
Semiconductor devices including an active fin and a drift region May 29, 2017 Issued
Array ( [id] => 13470321 [patent_doc_number] => 20180286703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => Laminated Member [patent_app_type] => utility [patent_app_number] => 15/608274 [patent_app_country] => US [patent_app_date] => 2017-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4129 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15608274 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/608274
Laminated member May 29, 2017 Issued
Array ( [id] => 16609545 [patent_doc_number] => 10910561 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-02 [patent_title] => Reduced diffusion in metal electrode for two-terminal memory [patent_app_type] => utility [patent_app_number] => 15/587560 [patent_app_country] => US [patent_app_date] => 2017-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11099 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15587560 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/587560
Reduced diffusion in metal electrode for two-terminal memory May 4, 2017 Issued
Array ( [id] => 13071141 [patent_doc_number] => 10056356 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-21 [patent_title] => Chip package circuit board module [patent_app_type] => utility [patent_app_number] => 15/585166 [patent_app_country] => US [patent_app_date] => 2017-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3362 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15585166 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/585166
Chip package circuit board module May 2, 2017 Issued
Array ( [id] => 13485447 [patent_doc_number] => 20180294266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => SEMICONDUCTOR DEVICE HAVING INSULATING LAYER HIGHER THAN A TOP SURFACE OF THE SUBSTRATE, AND METHOD FOR REDUCING THE DIFFICULTY OF FILLING AN INSULATING LAYER IN A RECESS [patent_app_type] => utility [patent_app_number] => 15/585180 [patent_app_country] => US [patent_app_date] => 2017-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3167 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15585180 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/585180
Semiconductor device having insulating layer higher than a top surface of the substrate, and method for reducing the difficulty of filling an insulating layer in a recess May 2, 2017 Issued
Array ( [id] => 13243053 [patent_doc_number] => 10134736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => Method of integrating thyristor and metal-oxide semiconductor transistor on a semiconductor substrate [patent_app_type] => utility [patent_app_number] => 15/493150 [patent_app_country] => US [patent_app_date] => 2017-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3876 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15493150 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/493150
Method of integrating thyristor and metal-oxide semiconductor transistor on a semiconductor substrate Apr 20, 2017 Issued
Array ( [id] => 11840295 [patent_doc_number] => 20170222015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'EPI FACET HEIGHT UNIFORMITY IMPROVEMENT FOR FDSOI TECHNOLOGIES' [patent_app_type] => utility [patent_app_number] => 15/490180 [patent_app_country] => US [patent_app_date] => 2017-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3140 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15490180 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/490180
Epi facet height uniformity improvement for FDSOI technologies Apr 17, 2017 Issued
Array ( [id] => 11760246 [patent_doc_number] => 20170207115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'DUAL ISOLATION FIN AND METHOD OF MAKING' [patent_app_type] => utility [patent_app_number] => 15/478793 [patent_app_country] => US [patent_app_date] => 2017-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4239 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15478793 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/478793
Dual isolation fin and method of making Apr 3, 2017 Issued
Array ( [id] => 12160623 [patent_doc_number] => 20180031890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-01 [patent_title] => 'DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/463847 [patent_app_country] => US [patent_app_date] => 2017-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 9656 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15463847 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/463847
Display device and method of manufacturing the same Mar 19, 2017 Issued
Array ( [id] => 13121743 [patent_doc_number] => 10079228 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-09-18 [patent_title] => Tight integrated vertical transistor dual diode structure for electrostatic discharge circuit protector [patent_app_type] => utility [patent_app_number] => 15/463795 [patent_app_country] => US [patent_app_date] => 2017-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 10504 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15463795 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/463795
Tight integrated vertical transistor dual diode structure for electrostatic discharge circuit protector Mar 19, 2017 Issued
Array ( [id] => 15315307 [patent_doc_number] => 10522367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Gettering layer formation and substrate [patent_app_type] => utility [patent_app_number] => 15/450605 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8042 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15450605 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/450605
Gettering layer formation and substrate Mar 5, 2017 Issued
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