Search

Dang T. Ton

Examiner (ID: 7746, Phone: (571)272-3171 , Office: P/2476 )

Most Active Art Unit
2476
Art Unit(s)
2476, 2661, OPT, 2603, 2666, 2616, 2899, 2732, 2475
Total Applications
2064
Issued Applications
1715
Pending Applications
214
Abandoned Applications
162

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16418109 [patent_doc_number] => 10826012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Light-emitting display device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/994555 [patent_app_country] => US [patent_app_date] => 2018-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 9374 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15994555 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/994555
Light-emitting display device and manufacturing method thereof May 30, 2018 Issued
Array ( [id] => 14446871 [patent_doc_number] => 20190181309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => CUTTING METHOD OF SEMICONDUCTOR PACKAGE MODULE AND SEMICONDUCTOR PACKAGE UNIT [patent_app_type] => utility [patent_app_number] => 15/993620 [patent_app_country] => US [patent_app_date] => 2018-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6051 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15993620 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/993620
CUTTING METHOD OF SEMICONDUCTOR PACKAGE MODULE AND SEMICONDUCTOR PACKAGE UNIT May 30, 2018 Abandoned
Array ( [id] => 15217947 [patent_doc_number] => 20190371660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => BARRIER LAYER FORMATION FOR CONDUCTIVE FEATURE [patent_app_type] => utility [patent_app_number] => 15/993751 [patent_app_country] => US [patent_app_date] => 2018-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9862 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15993751 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/993751
Barrier layer formation for conductive feature May 30, 2018 Issued
Array ( [id] => 14476037 [patent_doc_number] => 20190189667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => FAN-OUT SENSOR PACKAGE [patent_app_type] => utility [patent_app_number] => 15/982676 [patent_app_country] => US [patent_app_date] => 2018-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15982676 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/982676
Fan-out sensor package May 16, 2018 Issued
Array ( [id] => 16067705 [patent_doc_number] => 10692816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Semiconductor packages including die over-shift indicating patterns [patent_app_type] => utility [patent_app_number] => 15/981603 [patent_app_country] => US [patent_app_date] => 2018-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6176 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15981603 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/981603
Semiconductor packages including die over-shift indicating patterns May 15, 2018 Issued
Array ( [id] => 13419983 [patent_doc_number] => 20180261534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => Through Vias and Methods of Formation Thereof [patent_app_type] => utility [patent_app_number] => 15/981662 [patent_app_country] => US [patent_app_date] => 2018-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6110 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15981662 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/981662
Through vias and methods of formation thereof May 15, 2018 Issued
Array ( [id] => 13405421 [patent_doc_number] => 20180254253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-06 [patent_title] => Package with Different Types of Semiconductor Dies Attached to a Flange [patent_app_type] => utility [patent_app_number] => 15/973276 [patent_app_country] => US [patent_app_date] => 2018-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4957 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15973276 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/973276
Package with different types of semiconductor dies attached to a flange May 6, 2018 Issued
Array ( [id] => 16180440 [patent_doc_number] => 20200227409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/624166 [patent_app_country] => US [patent_app_date] => 2018-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8861 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16624166 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/624166
Semiconductor device Apr 15, 2018 Issued
Array ( [id] => 13349867 [patent_doc_number] => 20180226473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/943147 [patent_app_country] => US [patent_app_date] => 2018-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15943147 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/943147
Method of manufacturing a semiconductor device Apr 1, 2018 Issued
Array ( [id] => 14333219 [patent_doc_number] => 10297638 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-21 [patent_title] => Flexible light source structure and method for manufacturing same [patent_app_type] => utility [patent_app_number] => 15/920596 [patent_app_country] => US [patent_app_date] => 2018-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2167 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15920596 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/920596
Flexible light source structure and method for manufacturing same Mar 13, 2018 Issued
Array ( [id] => 14875353 [patent_doc_number] => 20190287918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => INTEGRATED CIRCUIT (IC) PACKAGES WITH SHIELDS AND METHODS OF PRODUCING THE SAME [patent_app_type] => utility [patent_app_number] => 15/920242 [patent_app_country] => US [patent_app_date] => 2018-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3652 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15920242 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/920242
INTEGRATED CIRCUIT (IC) PACKAGES WITH SHIELDS AND METHODS OF PRODUCING THE SAME Mar 12, 2018 Abandoned
Array ( [id] => 16959264 [patent_doc_number] => 11063148 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-13 [patent_title] => High voltage depletion mode MOS device with adjustable threshold voltage and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/909277 [patent_app_country] => US [patent_app_date] => 2018-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5446 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 620 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15909277 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/909277
High voltage depletion mode MOS device with adjustable threshold voltage and manufacturing method thereof Feb 28, 2018 Issued
Array ( [id] => 12895960 [patent_doc_number] => 20180190495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => ORGANIC THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING ORGANIC THIN FILM TRANSISTOR [patent_app_type] => utility [patent_app_number] => 15/909746 [patent_app_country] => US [patent_app_date] => 2018-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10934 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15909746 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/909746
Organic thin film transistor and method for manufacturing organic thin film transistor Feb 28, 2018 Issued
Array ( [id] => 16218532 [patent_doc_number] => 10734354 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Semiconductor device including optically connected wafer stack [patent_app_type] => utility [patent_app_number] => 15/906102 [patent_app_country] => US [patent_app_date] => 2018-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 4994 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15906102 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/906102
Semiconductor device including optically connected wafer stack Feb 26, 2018 Issued
Array ( [id] => 15234243 [patent_doc_number] => 10504851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-10 [patent_title] => Structure and method to improve overlay performance in semiconductor devices [patent_app_type] => utility [patent_app_number] => 15/904853 [patent_app_country] => US [patent_app_date] => 2018-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5624 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15904853 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/904853
Structure and method to improve overlay performance in semiconductor devices Feb 25, 2018 Issued
Array ( [id] => 12873046 [patent_doc_number] => 20180182857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/901343 [patent_app_country] => US [patent_app_date] => 2018-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12310 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15901343 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/901343
Semiconductor device and manufacturing method thereof Feb 20, 2018 Issued
Array ( [id] => 16372472 [patent_doc_number] => 10804238 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Semiconductor device having an electrical connection between semiconductor chips established by wire bonding, and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/901335 [patent_app_country] => US [patent_app_date] => 2018-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3360 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15901335 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/901335
Semiconductor device having an electrical connection between semiconductor chips established by wire bonding, and method for manufacturing the same Feb 20, 2018 Issued
Array ( [id] => 12872737 [patent_doc_number] => 20180182754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/900810 [patent_app_country] => US [patent_app_date] => 2018-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14022 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -36 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15900810 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/900810
Semiconductor device including trenches formed in transistor or diode portions Feb 20, 2018 Issued
Array ( [id] => 13950873 [patent_doc_number] => 10211215 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-19 [patent_title] => Three-dimensional memory device containing word lines having vertical protrusion regions and methods of making the same [patent_app_type] => utility [patent_app_number] => 15/895102 [patent_app_country] => US [patent_app_date] => 2018-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 61 [patent_figures_cnt] => 65 [patent_no_of_words] => 25832 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15895102 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/895102
Three-dimensional memory device containing word lines having vertical protrusion regions and methods of making the same Feb 12, 2018 Issued
Array ( [id] => 16418019 [patent_doc_number] => 10825921 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Lateral bipolar junction transistor with controlled junction [patent_app_type] => utility [patent_app_number] => 15/894273 [patent_app_country] => US [patent_app_date] => 2018-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7977 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15894273 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/894273
Lateral bipolar junction transistor with controlled junction Feb 11, 2018 Issued
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